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sawg: expose config channel
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@ -1,4 +1,160 @@
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from artiq.language.types import TInt32, TBool
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from artiq.language.core import kernel, now_mu
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from artiq.coredevice.spline import Spline
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from artiq.coredevice.rtio import rtio_output
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# sawg.Config addresses
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_SAWG_DIV = 0
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_SAWG_CLR = 1
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_SAWG_IQ_EN = 2
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# _SAWF_PAD = 3 # reserved
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_SAWG_DUC_I_MIN = 4
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_SAWG_DUC_I_MAX = 5
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_SAWG_DUC_Q_MIN = 6
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_SAWG_DUC_Q_MAX = 7
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_SAWG_OUT_MIN = 8
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_SAWG_OUT_MAX = 9
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class Config:
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"""SAWG configuration.
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Exposes the configurable quantities of a single SAWG channel.
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:param channel: RTIO channel number of the channel.
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:param core: Core device.
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"""
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kernel_invariants = {"channel", "core"}
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def __init__(self, channel, core):
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self.channel = channel
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self.core = core
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@kernel
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def set_div(self, div: TInt32, n: TInt32=0):
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"""Set the spline evolution divider and current counter value.
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The divider and the spline evolution are synchronized across all
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spline channels within a SAWG channel. The phase accumulator always
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evolves at full speed.
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:param div: Spline evolution divider, such that
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``t_sawg_spline/t_rtio_coarse = div + 1``. Default: ``0``.
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:param n: Current value of the counter. Default: ``0``.
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"""
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rtio_output(now_mu(), self.channel, _SAWG_DIV, div | (n << 16))
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@kernel
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def set_clr(self, clr0: TBool, clr1: TBool, clr2: TBool):
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"""Set the phase clear mode for the three phase accumulators.
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When the ``clr`` bit for a given phase accumulator is
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set, that phase accumulator will be cleared with every phase RTIO
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command and the output phase will be exactly the phase RTIO value
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("absolute phase update mode").
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In turn, when the bit is cleared, the phase RTIO channels only
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provide a phase offset to the current value of the phase
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accumulator ("relative phase update mode").
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:param clr0: Auto-clear phase accumulator of the ``phase0``/
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``frequency0`` DUC. Default: ``True``
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:param clr1: Auto-clear phase accumulator of the ``phase1``/
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``frequency1`` DDS. Default: ``True``
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:param clr2: Auto-clear phase accumulator of the ``phase2``/
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``frequency2`` DDS. Default: ``True``
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"""
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rtio_output(now_mu(), self.channel, _SAWG_CLR, int(clr1) |
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(int(clr2) << 1) | (int(clr0) << 2))
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@kernel
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def set_iq_en(self, i_enable: TBool, q_enable: TBool):
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"""Enable I/Q data on this DAC channel.
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Every pair of SAWG channels forms a buddy pair.
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The ``iq_en`` configuration controls which DDS data is emitted to the
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DACs.
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Refer to the documentation of :class:`SAWG` for a mathematical
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description of ``i_enable`` and ``q_enable``.
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:param i_enable: Controls adding the in-phase
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DUC-DDS data of *this* SAWG channel to *this* DAC channel.
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Default: ``1``.
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:param q_enable: controls adding the quadrature
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DUC-DDS data of this SAWG's *buddy* channel to *this* DAC
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channel. Default: ``0``.
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"""
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rtio_output(now_mu(), self.channel, _SAWG_IQ_EN, int(i_enable) |
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(int(q_enable) << 1))
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@kernel
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def set_duc_i_max(self, limit: TInt32):
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"""Set the DUC I data summing junction upper limit.
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Each of the three summing junctions has a saturating adder with
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configurable upper and lower limits. The three summing junctions are:
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* At the in-phase input to the ``phase0``/``frequency0`` fast DUC,
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where the in-phase outputs of the two slow DDS (1 and 2) are
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added together.
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* At the quadrature input to the ``phase0``/``frequency0``
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fast DUC, where the quadrature outputs of the two slow DDS
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(1 and 2) are added together.
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* Before the DAC, where the following three data streams
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are added together:
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* the output of the ``offset`` spline,
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* (optionally, depending on ``i_enable``) the in-phase output
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of the ``phase0``/``frequency0`` fast DUC, and
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* (optionally, depending on ``q_enable``) the quadrature
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output of the ``phase0``/``frequency0`` fast DUC of the
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buddy channel.
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Refer to the documentation of :class:`SAWG` for a mathematical
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description of the summing junctions.
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The default limits are the full range of signed 16 bit data.
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.. seealso::
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* :meth:`set_duc_i_max`: Upper limit of the in-phase input to
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the DUC.
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* :meth:`set_duc_i_min`: Lower limit of the in-phase input to
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the DUC.
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* :meth:`set_duc_q_max`: Upper limit of the quadrature input to
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the DUC.
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* :meth:`set_duc_q_min`: Lower limit of the quadrature input to
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the DUC.
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* :meth:`set_out_max`: Upper limit of the DAC output.
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* :meth:`set_out_min`: Lower limit of the DAC output.
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"""
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rtio_output(now_mu(), self.channel, _SAWG_DUC_I_MAX, limit)
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@kernel
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def set_duc_i_min(self, limit: TInt32):
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""".. seealso:: :meth:`set_duc_i_max`"""
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rtio_output(now_mu(), self.channel, _SAWG_DUC_I_MIN, limit)
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@kernel
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def set_duc_q_max(self, limit: TInt32):
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""".. seealso:: :meth:`set_duc_i_max`"""
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rtio_output(now_mu(), self.channel, _SAWG_DUC_Q_MAX, limit)
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@kernel
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def set_duc_q_min(self, limit: TInt32):
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""".. seealso:: :meth:`set_duc_i_max`"""
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rtio_output(now_mu(), self.channel, _SAWG_DUC_Q_MIN, limit)
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@kernel
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def set_out_max(self, limit: TInt32):
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""".. seealso:: :meth:`set_duc_i_max`"""
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rtio_output(now_mu(), self.channel, _SAWG_OUT_MAX, limit)
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@kernel
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def set_out_min(self, limit: TInt32):
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""".. seealso:: :meth:`set_duc_i_max`"""
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rtio_output(now_mu(), self.channel, _SAWG_OUT_MIN, limit)
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class SAWG:
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@ -13,8 +169,10 @@ class SAWG:
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i_enable*Re(oscillators) +
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q_enable*Im(buddy_oscillators))
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The nine spline interpolators are accessible as attributes:
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The configuration channel and the nine spline interpolators are accessible
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as attributes:
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* :attr:`config`: :class:`Config`
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* :attr:`offset`, :attr:`amplitude1`, :attr:`amplitude2`: in units
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of full scale
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* :attr:`phase0`, :attr:`phase1`, :attr:`phase2`: in units of turns
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@ -22,7 +180,8 @@ class SAWG:
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of Hz
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:param channel_base: RTIO channel number of the first channel (amplitude).
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Frequency and Phase are then assumed to be successive channels.
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The configuration channel and frequency/phase/amplitude channels are
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then assumed to be successive channels.
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:param parallelism: Number of output samples per coarse RTIO clock cycle.
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:param core_device: Name of the core device that this SAWG is on.
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"""
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@ -37,7 +196,7 @@ class SAWG:
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width = 16
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time_width = 16
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cordic_gain = 1.646760258057163 # Cordic(width=16, guard=None).gain
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# cfg: channel_base
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self.config = Config(channel_base, self.core)
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self.offset = Spline(width, time_width, channel_base + 1,
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self.core, 2.)
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self.amplitude1 = Spline(width, time_width, channel_base + 2,
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@ -17,6 +17,21 @@ class SAWGTestTwoTone(EnvExperiment):
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self.core.reset()
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self.ttl_sma.output()
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self.sawg0.config.set_clr(True, True, True)
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delay(10*us)
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self.sawg0.config.set_duc_i_max(0x7fff)
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delay(10*us)
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self.sawg0.config.set_duc_i_min(-0x8000)
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delay(10*us)
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self.sawg0.config.set_duc_q_max(0x7fff)
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delay(10*us)
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self.sawg0.config.set_duc_q_min(-0x8000)
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delay(10*us)
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self.sawg0.config.set_out_max(0x7fff)
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delay(10*us)
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self.sawg0.config.set_out_min(-0x8000)
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delay(10*us)
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while True:
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t_up = t_hold = t_down = 800*ns
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a1 = .3
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