From 0a9f69a3ed4de738ea66eab3e9456b6e7eada840 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Fri, 9 Dec 2016 19:23:36 +0800 Subject: [PATCH] kc705_drtio_master: add missing rtio_core CSRs --- artiq/gateware/targets/kc705_drtio_master.py | 1 + 1 file changed, 1 insertion(+) diff --git a/artiq/gateware/targets/kc705_drtio_master.py b/artiq/gateware/targets/kc705_drtio_master.py index e8ea943e7..d3ad0a6ed 100755 --- a/artiq/gateware/targets/kc705_drtio_master.py +++ b/artiq/gateware/targets/kc705_drtio_master.py @@ -100,6 +100,7 @@ class Master(MiniSoC, AMPSoC): self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) self.submodules.rtio_core = rtio.Core(rtio_channels, 3) + self.csr_devices.append("rtio_core") self.submodules.rtio = rtio.KernelInitiator() self.submodules.rtio_dma = rtio.DMA(self.get_native_sdram_if())