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Merge pull request #832 from mntng/master

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set range for divider values
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Robert Jördens 2017-09-21 08:43:43 +02:00 committed by GitHub
commit 0a43815956
1 changed files with 2 additions and 0 deletions
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artiq/coredevice/spi.py
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@ -155,6 +155,8 @@ class SPIMaster:
by one RTIO clock cycle.
:param read_div: Ditto for the read clock.
"""
if write_div > 257 or write_div < 2 or read_div > 257 or read_div < 2:
raise ValueError('Divider values out of range')
rtio_output(now_mu(), self.channel, SPI_CONFIG_ADDR, flags |
((write_div - 2) << 16) | ((read_div - 2) << 24))
self.write_period_mu = int(write_div*self.ref_period_mu)