From e94d2d37797b1693e7818a764854f69c8512f51a Mon Sep 17 00:00:00 2001 From: Thao Date: Thu, 21 Sep 2017 14:26:16 +0800 Subject: [PATCH] set range for divider values --- artiq/coredevice/spi.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/artiq/coredevice/spi.py b/artiq/coredevice/spi.py index 5c2461216..f9c47f5e7 100644 --- a/artiq/coredevice/spi.py +++ b/artiq/coredevice/spi.py @@ -155,6 +155,8 @@ class SPIMaster: by one RTIO clock cycle. :param read_div: Ditto for the read clock. """ + if write_div > 257 or write_div < 2 or read_div > 257 or read_div < 2: + raise ValueError('Divider values out of range') rtio_output(now_mu(), self.channel, SPI_CONFIG_ADDR, flags | ((write_div - 2) << 16) | ((read_div - 2) << 24)) self.write_period_mu = int(write_div*self.ref_period_mu)