mirror of https://github.com/m-labs/artiq.git
runtime: monitor RTIO clock status
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@ -26,6 +26,16 @@ long long int clock_get_ms(void)
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return clock_ms;
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}
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void busywait_us(long long int us)
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{
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long long int threshold;
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timer0_update_value_write(1);
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threshold = timer0_value_read() - us*(long long int)identifier_frequency_read()/1000000LL;
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while(timer0_value_read() > threshold)
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timer0_update_value_write(1);
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}
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struct watchdog {
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int active;
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long long int threshold;
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@ -3,6 +3,7 @@
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void clock_init(void);
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long long int clock_get_ms(void);
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void busywait_us(long long us);
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#define MAX_WATCHDOGS 16
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@ -128,20 +128,30 @@ static int check_flash_storage_key_len(char *key, unsigned int key_len)
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return 1;
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}
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static void switch_clock(int clk)
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static int switch_clock(int clk)
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{
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int current_clk;
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current_clk = rtio_crg_clock_sel_read();
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if(clk == current_clk)
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return;
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if(clk == current_clk) {
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#ifdef CSR_RTIO_CRG_PLL_RESET_ADDR
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busywait_us(150);
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if(!rtio_crg_pll_locked_read())
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return 0;
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#endif
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return 1;
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}
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#ifdef CSR_RTIO_CRG_PLL_RESET_ADDR
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rtio_crg_pll_reset_write(1);
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#endif
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rtio_crg_clock_sel_write(clk);
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#ifdef CSR_RTIO_CRG_PLL_RESET_ADDR
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rtio_crg_pll_reset_write(0);
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busywait_us(150);
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if(!rtio_crg_pll_locked_read())
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return 0;
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#endif
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return 1;
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}
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static int process_input(void)
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@ -170,8 +180,10 @@ static int process_input(void)
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submit_output(9);
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break;
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}
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switch_clock(buffer_in[9]);
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if(switch_clock(buffer_in[9]))
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buffer_out[8] = REMOTEMSG_TYPE_CLOCK_SWITCH_COMPLETED;
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else
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buffer_out[8] = REMOTEMSG_TYPE_CLOCK_SWITCH_FAILED;
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submit_output(9);
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break;
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case REMOTEMSG_TYPE_LOAD_OBJECT:
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@ -543,11 +555,20 @@ void session_poll(void **data, int *len)
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{
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int l;
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if((user_kernel_state == USER_KERNEL_RUNNING) && watchdog_expired()) {
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if(user_kernel_state == USER_KERNEL_RUNNING) {
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if(watchdog_expired()) {
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log("Watchdog expired");
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*len = -1;
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return;
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}
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#ifdef CSR_RTIO_CRG_PLL_RESET_ADDR
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if(!rtio_crg_pll_locked_read()) {
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log("RTIO clock failure");
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*len = -1;
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return;
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}
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#endif
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}
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l = get_out_packet_len();
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