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drtio: aux controller unittest
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@ -1,4 +1,5 @@
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import unittest
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import random
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from types import SimpleNamespace
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from migen import *
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@ -42,7 +43,7 @@ class TestAuxController(unittest.TestCase):
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def test_aux_controller(self):
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dut = TB(4)
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def gen():
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def link_init():
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yield dut.link_layer.tx.link_init.eq(1)
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yield
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yield
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@ -52,16 +53,49 @@ class TestAuxController(unittest.TestCase):
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while (yield dut.link_layer.rx.link_init):
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yield
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yield dut.link_layer.ready.eq(1)
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yield
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yield from dut.aux_controller.bus.write(0, 0x42)
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yield from dut.aux_controller.bus.write(1, 0x23)
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yield from dut.aux_controller.transmitter.aux_tx_length.write(8)
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def send_packet(packet):
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for i, d in enumerate(packet):
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yield from dut.aux_controller.bus.write(i, d)
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yield from dut.aux_controller.transmitter.aux_tx_length.write(len(packet)*4)
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yield from dut.aux_controller.transmitter.aux_tx.write(1)
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for i in range(40):
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yield
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while (yield from dut.aux_controller.transmitter.aux_tx.read()):
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yield
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print(hex((yield from dut.aux_controller.bus.read(256))))
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print(hex((yield from dut.aux_controller.bus.read(257))))
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print((yield from dut.aux_controller.receiver.aux_rx_length.read()))
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run_simulation(dut, gen(), vcd_name="foo.vcd")
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def receive_packet():
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while not (yield from dut.aux_controller.receiver.aux_rx_present.read()):
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yield
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length = yield from dut.aux_controller.receiver.aux_rx_length.read()
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r = []
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for i in range(length//4):
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r.append((yield from dut.aux_controller.bus.read(256+i)))
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yield from dut.aux_controller.receiver.aux_rx_present.write(1)
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return r
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prng = random.Random(0)
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def send_and_check_packet():
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data = [prng.randrange(2**32-1) for _ in range(prng.randrange(1, 16))]
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yield from send_packet(data)
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received = yield from receive_packet()
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self.assertEqual(data, received)
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def sim():
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yield from link_init()
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for i in range(8):
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yield from send_and_check_packet()
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@passive
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def rt_traffic():
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while True:
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while prng.randrange(4):
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yield
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yield dut.link_layer.tx_rt_frame.eq(1)
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yield
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while prng.randrange(4):
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yield
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yield dut.link_layer.tx_rt_frame.eq(0)
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yield
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run_simulation(dut, [sim(), rt_traffic()])
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