M-Labs
/
artiq
mirror of https://github.com/m-labs/artiq.git
2
0
Fork 2
Code Issues Projects Releases Wiki Activity

rtio/wishbone: support write-only interface

This commit is contained in:
Sebastien Bourdeauducq 2018-11-26 07:38:06 +08:00
parent 450a035f9e
commit 09141e5bee
1 changed files with 10 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
artiq/gateware/rtio/phy/wishbone.py
View File

@ -5,18 +5,18 @@ from artiq.gateware.rtio import rtlink
class RT2WB(Module):
def __init__(self, address_width, wb=None, rtio_enable_replace=False):
def __init__(self, address_width, wb=None, rtio_enable_replace=False, write_only=False):
if wb is None:
wb = wishbone.Interface()
self.wb = wb
self.rtlink = rtlink.Interface(
rtlink.OInterface(
len(wb.dat_w),
address_width + 1,
address_width + 1 if not write_only else address_width,
enable_replace=rtio_enable_replace),
rtlink.IInterface(
len(wb.dat_r),
timestamped=False)
timestamped=False) if not write_only else None
)
# # #
@ -26,7 +26,7 @@ class RT2WB(Module):
If(self.rtlink.o.stb,
active.eq(1),
wb.adr.eq(self.rtlink.o.address[:address_width]),
wb.we.eq(~self.rtlink.o.address[address_width]),
wb.we.eq(~self.rtlink.o.address[address_width] if not write_only else 1),
wb.dat_w.eq(self.rtlink.o.data),
wb.sel.eq(2**len(wb.sel) - 1)
),
@ -38,7 +38,10 @@ class RT2WB(Module):
self.rtlink.o.busy.eq(active),
wb.cyc.eq(active),
wb.stb.eq(active),
self.rtlink.i.stb.eq(wb.ack & ~wb.we),
self.rtlink.i.data.eq(wb.dat_r)
]
if not write_only:
self.comb += [
self.rtlink.i.stb.eq(wb.ack & ~wb.we),
self.rtlink.i.data.eq(wb.dat_r)
]