mirror of https://github.com/m-labs/artiq.git
update NAC3, use new Kernel type annotation
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parent
d853604380
commit
088c3b470e
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@ -10,7 +10,7 @@ time is an error.
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from numpy import int32, int64
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from numpy import int32, int64
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from artiq.language.core import nac3, kernel, portable, KernelInvariant
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from artiq.language.core import nac3, kernel, portable, Kernel, KernelInvariant
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from artiq.language.units import ns, us
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from artiq.language.units import ns, us
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from artiq.coredevice.core import Core
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from artiq.coredevice.core import Core
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from artiq.coredevice.ttl import TTLOut
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from artiq.coredevice.ttl import TTLOut
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@ -150,7 +150,7 @@ class AD53xx:
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div_write: KernelInvariant[int32]
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div_write: KernelInvariant[int32]
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div_read: KernelInvariant[int32]
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div_read: KernelInvariant[int32]
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vref: KernelInvariant[float]
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vref: KernelInvariant[float]
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offset_dacs: int32
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offset_dacs: Kernel[int32]
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def __init__(self, dmgr, spi_device, ldac_device=None, clr_device=None,
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def __init__(self, dmgr, spi_device, ldac_device=None, clr_device=None,
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chip_select=1, div_write=4, div_read=16, vref=5.,
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chip_select=1, div_write=4, div_read=16, vref=5.,
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@ -11,7 +11,7 @@ on Mirny-style prefixed SPI buses.
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from numpy import int32, int64
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from numpy import int32, int64
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from math import floor, ceil
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from math import floor, ceil
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from artiq.language.core import nac3, KernelInvariant, kernel, portable, round64
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from artiq.language.core import nac3, Kernel, KernelInvariant, kernel, portable, round64
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from artiq.language.units import us, GHz, MHz
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from artiq.language.units import us, GHz, MHz
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from artiq.coredevice.core import Core
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from artiq.coredevice.core import Core
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from artiq.coredevice.mirny import Mirny
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from artiq.coredevice.mirny import Mirny
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@ -58,9 +58,9 @@ class ADF5356:
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channel: KernelInvariant[int32]
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channel: KernelInvariant[int32]
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sw: KernelInvariant[TTLOut]
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sw: KernelInvariant[TTLOut]
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sysclk: KernelInvariant[float]
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sysclk: KernelInvariant[float]
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regs: list[int32]
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regs: Kernel[list[int32]]
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ref_doubler: bool
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ref_doubler: Kernel[bool]
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ref_divider: bool
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ref_divider: Kernel[bool]
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def __init__(
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def __init__(
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self,
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self,
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@ -1,7 +1,7 @@
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"""RTIO driver for Mirny (4 channel GHz PLLs)
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"""RTIO driver for Mirny (4 channel GHz PLLs)
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"""
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"""
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from artiq.language.core import nac3, KernelInvariant, kernel
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from artiq.language.core import nac3, Kernel, KernelInvariant, kernel
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from artiq.language.units import us
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from artiq.language.units import us
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from numpy import int32
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from numpy import int32
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@ -51,9 +51,9 @@ class Mirny:
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core: KernelInvariant[Core]
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core: KernelInvariant[Core]
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bus: KernelInvariant[SPIMaster]
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bus: KernelInvariant[SPIMaster]
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refclk: KernelInvariant[float]
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refclk: KernelInvariant[float]
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clk_sel_hw_rev: list[int32]
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clk_sel_hw_rev: Kernel[list[int32]]
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hw_rev: int32
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hw_rev: Kernel[int32]
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clk_sel: int32
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clk_sel: Kernel[int32]
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def __init__(self, dmgr, spi_device, refclk=100e6, clk_sel="XO", core_device="core"):
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def __init__(self, dmgr, spi_device, refclk=100e6, clk_sel="XO", core_device="core"):
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self.core = dmgr.get(core_device)
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self.core = dmgr.get(core_device)
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@ -9,7 +9,7 @@ time is an error.
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from numpy import int32, int64
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from numpy import int32, int64
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from artiq.language.core import nac3, KernelInvariant, kernel, portable, extern
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from artiq.language.core import nac3, Kernel, KernelInvariant, kernel, portable, extern
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from artiq.coredevice.core import Core
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from artiq.coredevice.core import Core
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from artiq.coredevice.rtio import rtio_output, rtio_input_data
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from artiq.coredevice.rtio import rtio_output, rtio_input_data
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@ -68,7 +68,7 @@ class SPIMaster:
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core: KernelInvariant[Core]
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core: KernelInvariant[Core]
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ref_period_mu: KernelInvariant[int64]
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ref_period_mu: KernelInvariant[int64]
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channel: KernelInvariant[int32]
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channel: KernelInvariant[int32]
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xfer_duration_mu: int64
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xfer_duration_mu: Kernel[int64]
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def __init__(self, dmgr, channel, div=0, length=0, core_device="core"):
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def __init__(self, dmgr, channel, div=0, length=0, core_device="core"):
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self.core = dmgr.get(core_device)
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self.core = dmgr.get(core_device)
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@ -1,6 +1,6 @@
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from numpy import int32, int64
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from numpy import int32, int64
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from artiq.language.core import nac3, KernelInvariant, kernel, portable
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from artiq.language.core import nac3, Kernel, KernelInvariant, kernel, portable
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from artiq.language.units import us, ms
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from artiq.language.units import us, ms
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from artiq.coredevice.core import Core
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from artiq.coredevice.core import Core
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@ -157,9 +157,9 @@ class CPLD:
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io_update: KernelInvariant[TTLOut]
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io_update: KernelInvariant[TTLOut]
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clk_div: KernelInvariant[int32]
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clk_div: KernelInvariant[int32]
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sync: KernelInvariant[_DummySync]
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sync: KernelInvariant[_DummySync]
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cfg_reg: int32
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cfg_reg: Kernel[int32]
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att_reg: int32
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att_reg: Kernel[int32]
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sync_div: int32
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sync_div: Kernel[int32]
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def __init__(self, dmgr, spi_device, io_update_device=None,
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def __init__(self, dmgr, spi_device, io_update_device=None,
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dds_reset_device=None, sync_device=None,
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dds_reset_device=None, sync_device=None,
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@ -12,7 +12,7 @@ from artiq.language import import_cache
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__all__ = [
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__all__ = [
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"KernelInvariant", "virtual",
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"Kernel", "KernelInvariant", "virtual",
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"round64", "floor64", "ceil64",
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"round64", "floor64", "ceil64",
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"extern", "kernel", "portable", "nac3", "rpc",
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"extern", "kernel", "portable", "nac3", "rpc",
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"parallel", "sequential",
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"parallel", "sequential",
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@ -22,6 +22,9 @@ __all__ = [
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T = TypeVar('T')
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T = TypeVar('T')
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class Kernel(Generic[T]):
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pass
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class KernelInvariant(Generic[T]):
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class KernelInvariant(Generic[T]):
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pass
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pass
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