diff --git a/artiq/coredevice/ad53xx.py b/artiq/coredevice/ad53xx.py
index f8bbc76bb..0abfd76d9 100644
--- a/artiq/coredevice/ad53xx.py
+++ b/artiq/coredevice/ad53xx.py
@@ -10,7 +10,7 @@ time is an error.
 
 from numpy import int32, int64
 
-from artiq.language.core import nac3, kernel, portable, KernelInvariant
+from artiq.language.core import nac3, kernel, portable, Kernel, KernelInvariant
 from artiq.language.units import ns, us
 from artiq.coredevice.core import Core
 from artiq.coredevice.ttl import TTLOut
@@ -150,7 +150,7 @@ class AD53xx:
     div_write: KernelInvariant[int32]
     div_read: KernelInvariant[int32]
     vref: KernelInvariant[float]
-    offset_dacs: int32
+    offset_dacs: Kernel[int32]
 
     def __init__(self, dmgr, spi_device, ldac_device=None, clr_device=None,
                  chip_select=1, div_write=4, div_read=16, vref=5.,
diff --git a/artiq/coredevice/adf5356.py b/artiq/coredevice/adf5356.py
index 1c6812219..e783c8088 100644
--- a/artiq/coredevice/adf5356.py
+++ b/artiq/coredevice/adf5356.py
@@ -11,7 +11,7 @@ on Mirny-style prefixed SPI buses.
 from numpy import int32, int64
 from math import floor, ceil
 
-from artiq.language.core import nac3, KernelInvariant, kernel, portable, round64
+from artiq.language.core import nac3, Kernel, KernelInvariant, kernel, portable, round64
 from artiq.language.units import us, GHz, MHz
 from artiq.coredevice.core import Core
 from artiq.coredevice.mirny import Mirny
@@ -58,9 +58,9 @@ class ADF5356:
     channel: KernelInvariant[int32]
     sw: KernelInvariant[TTLOut]
     sysclk: KernelInvariant[float]
-    regs: list[int32]
-    ref_doubler: bool
-    ref_divider: bool
+    regs: Kernel[list[int32]]
+    ref_doubler: Kernel[bool]
+    ref_divider: Kernel[bool]
 
     def __init__(
         self,
diff --git a/artiq/coredevice/mirny.py b/artiq/coredevice/mirny.py
index 364b71298..83e00eb2d 100644
--- a/artiq/coredevice/mirny.py
+++ b/artiq/coredevice/mirny.py
@@ -1,7 +1,7 @@
 """RTIO driver for Mirny (4 channel GHz PLLs)
 """
 
-from artiq.language.core import nac3, KernelInvariant, kernel
+from artiq.language.core import nac3, Kernel, KernelInvariant, kernel
 from artiq.language.units import us
 
 from numpy import int32
@@ -51,9 +51,9 @@ class Mirny:
     core: KernelInvariant[Core]
     bus: KernelInvariant[SPIMaster]
     refclk: KernelInvariant[float]
-    clk_sel_hw_rev: list[int32]
-    hw_rev: int32
-    clk_sel: int32
+    clk_sel_hw_rev: Kernel[list[int32]]
+    hw_rev: Kernel[int32]
+    clk_sel: Kernel[int32]
 
     def __init__(self, dmgr, spi_device, refclk=100e6, clk_sel="XO", core_device="core"):
         self.core = dmgr.get(core_device)
diff --git a/artiq/coredevice/spi2.py b/artiq/coredevice/spi2.py
index ae1bd2ef4..3b0147a6a 100644
--- a/artiq/coredevice/spi2.py
+++ b/artiq/coredevice/spi2.py
@@ -9,7 +9,7 @@ time is an error.
 
 from numpy import int32, int64
 
-from artiq.language.core import nac3, KernelInvariant, kernel, portable, extern
+from artiq.language.core import nac3, Kernel, KernelInvariant, kernel, portable, extern
 from artiq.coredevice.core import Core
 from artiq.coredevice.rtio import rtio_output, rtio_input_data
 
@@ -68,7 +68,7 @@ class SPIMaster:
     core: KernelInvariant[Core]
     ref_period_mu: KernelInvariant[int64]
     channel: KernelInvariant[int32]
-    xfer_duration_mu: int64
+    xfer_duration_mu: Kernel[int64]
 
     def __init__(self, dmgr, channel, div=0, length=0, core_device="core"):
         self.core = dmgr.get(core_device)
diff --git a/artiq/coredevice/urukul.py b/artiq/coredevice/urukul.py
index 21c3bbf34..9ca7751b1 100644
--- a/artiq/coredevice/urukul.py
+++ b/artiq/coredevice/urukul.py
@@ -1,6 +1,6 @@
 from numpy import int32, int64
 
-from artiq.language.core import nac3, KernelInvariant, kernel, portable
+from artiq.language.core import nac3, Kernel, KernelInvariant, kernel, portable
 from artiq.language.units import us, ms
 
 from artiq.coredevice.core import Core
@@ -157,9 +157,9 @@ class CPLD:
     io_update: KernelInvariant[TTLOut]
     clk_div: KernelInvariant[int32]
     sync: KernelInvariant[_DummySync]
-    cfg_reg: int32
-    att_reg: int32
-    sync_div: int32
+    cfg_reg: Kernel[int32]
+    att_reg: Kernel[int32]
+    sync_div: Kernel[int32]
 
     def __init__(self, dmgr, spi_device, io_update_device=None,
                  dds_reset_device=None, sync_device=None,
diff --git a/artiq/language/core.py b/artiq/language/core.py
index f2e9bc988..b9f5fe8a9 100644
--- a/artiq/language/core.py
+++ b/artiq/language/core.py
@@ -12,7 +12,7 @@ from artiq.language import import_cache
 
 
 __all__ = [
-    "KernelInvariant", "virtual",
+    "Kernel", "KernelInvariant", "virtual",
     "round64", "floor64", "ceil64",
     "extern", "kernel", "portable", "nac3", "rpc",
     "parallel", "sequential",
@@ -22,6 +22,9 @@ __all__ = [
 
 T = TypeVar('T')
 
+class Kernel(Generic[T]):
+    pass
+
 class KernelInvariant(Generic[T]):
     pass