From 04b2fd3e13ef70e26900b702b1084fb20af15c3b Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Wed, 10 Jan 2018 12:11:33 +0800 Subject: [PATCH] sayma: fix AD9154NoSAWG ramp clock domain --- artiq/gateware/targets/sayma_amc_standalone.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/artiq/gateware/targets/sayma_amc_standalone.py b/artiq/gateware/targets/sayma_amc_standalone.py index 7a4de3d3c..82fcfdc51 100755 --- a/artiq/gateware/targets/sayma_amc_standalone.py +++ b/artiq/gateware/targets/sayma_amc_standalone.py @@ -107,7 +107,7 @@ class AD9154NoSAWG(Module, AutoCSR): for i, conv in enumerate(self.jesd.core.sink.flatten()): ramp = Signal(16) - self.sync += ramp.eq(ramp + (1 << 9 + i)) + self.sync.rtio += ramp.eq(ramp + (1 << 9 + i)) self.comb += conv.eq(Cat(ramp for i in range(len(conv) // len(ramp))))