mirror of https://github.com/m-labs/artiq.git
suservo: sampler channels are reversed
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parent
7e299563df
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04240cdc08
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@ -11,7 +11,7 @@ class Servo(Module):
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self.submodules.iir = IIR(iir_p)
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self.submodules.iir = IIR(iir_p)
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self.submodules.dds = DDS(dds_pads, dds_p)
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self.submodules.dds = DDS(dds_pads, dds_p)
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for i, j, k, l in zip(self.adc.data, self.iir.adc,
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for i, j, k, l in zip(reversed(self.adc.data), self.iir.adc,
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self.iir.dds, self.dds.profile):
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self.iir.dds, self.dds.profile):
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self.comb += j.eq(i), l.eq(k)
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self.comb += j.eq(i), l.eq(k)
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@ -28,7 +28,7 @@ class ServoSim(servo.Servo):
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adc = 1
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adc = 1
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x0 = 0x0141
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x0 = 0x0141
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yield self.adc_tb.data[adc].eq(x0)
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yield self.adc_tb.data[-adc-1].eq(x0)
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channel = 3
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channel = 3
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yield self.iir.adc[channel].eq(adc)
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yield self.iir.adc[channel].eq(adc)
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yield self.iir.ctrl[channel].en_iir.eq(1)
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yield self.iir.ctrl[channel].en_iir.eq(1)
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