diff --git a/artiq/gateware/suservo/servo.py b/artiq/gateware/suservo/servo.py
index b2df44bc4..34b485d06 100644
--- a/artiq/gateware/suservo/servo.py
+++ b/artiq/gateware/suservo/servo.py
@@ -11,7 +11,7 @@ class Servo(Module):
         self.submodules.iir = IIR(iir_p)
         self.submodules.dds = DDS(dds_pads, dds_p)
 
-        for i, j, k, l in zip(self.adc.data, self.iir.adc,
+        for i, j, k, l in zip(reversed(self.adc.data), self.iir.adc,
                 self.iir.dds, self.dds.profile):
             self.comb += j.eq(i), l.eq(k)
 
diff --git a/artiq/gateware/test/suservo/test_servo.py b/artiq/gateware/test/suservo/test_servo.py
index efa706cd0..67fcdeb71 100644
--- a/artiq/gateware/test/suservo/test_servo.py
+++ b/artiq/gateware/test/suservo/test_servo.py
@@ -28,7 +28,7 @@ class ServoSim(servo.Servo):
 
         adc = 1
         x0 = 0x0141
-        yield self.adc_tb.data[adc].eq(x0)
+        yield self.adc_tb.data[-adc-1].eq(x0)
         channel = 3
         yield self.iir.adc[channel].eq(adc)
         yield self.iir.ctrl[channel].en_iir.eq(1)