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dds: phase computation fixes

This commit is contained in:
Sebastien Bourdeauducq 2015-06-19 11:01:43 -06:00
parent b8bb3d8ca7
commit 03fe71228b
3 changed files with 14 additions and 12 deletions
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24
soc/runtime/dds.c
View File

@ -55,26 +55,26 @@ static void dds_set_one(long long int now, long long int ref_time, int channel,
{ {
DDS_WRITE(DDS_GPIO, channel); DDS_WRITE(DDS_GPIO, channel);
if(phase_mode == PHASE_MODE_CONTINUOUS)
/* Do not clear phase accumulator on FUD */
DDS_WRITE(0x02, 0x00);
else
/* Clear phase accumulator on FUD */
DDS_WRITE(0x02, 0x40);
DDS_WRITE(DDS_FTW0, ftw & 0xff); DDS_WRITE(DDS_FTW0, ftw & 0xff);
DDS_WRITE(DDS_FTW1, (ftw >> 8) & 0xff); DDS_WRITE(DDS_FTW1, (ftw >> 8) & 0xff);
DDS_WRITE(DDS_FTW2, (ftw >> 16) & 0xff); DDS_WRITE(DDS_FTW2, (ftw >> 16) & 0xff);
DDS_WRITE(DDS_FTW3, (ftw >> 24) & 0xff); DDS_WRITE(DDS_FTW3, (ftw >> 24) & 0xff);
/* We assume that the RTIO clock is DDS SYNCLK */ /* We need the RTIO fine timestamp clock to be phase-locked
if(phase_mode == PHASE_MODE_TRACKING) * to DDS SYNCLK, and divided by an integer DDS_RTIO_CLK_RATIO.
pow += (ref_time >> RTIO_FINE_TS_WIDTH)*ftw >> 18; */
if(phase_mode != PHASE_MODE_CONTINUOUS) { if(phase_mode == PHASE_MODE_CONTINUOUS) {
/* Do not clear phase accumulator on FUD */
DDS_WRITE(0x02, 0x00);
} else {
long long int fud_time; long long int fud_time;
/* Clear phase accumulator on FUD */
DDS_WRITE(0x02, 0x40);
fud_time = now + 2*DURATION_WRITE; fud_time = now + 2*DURATION_WRITE;
pow -= ((ref_time - fud_time) >> RTIO_FINE_TS_WIDTH)*ftw >> 18; pow -= (ref_time - fud_time)*DDS_RTIO_CLK_RATIO*ftw >> 18;
if(phase_mode == PHASE_MODE_TRACKING)
pow += ref_time*DDS_RTIO_CLK_RATIO*ftw >> 18;
} }
DDS_WRITE(DDS_POW0, pow & 0xff); DDS_WRITE(DDS_POW0, pow & 0xff);

1
soc/targets/artiq_kc705.py
View File

@ -93,6 +93,7 @@ class NIST_QC1(MiniSoC, AMPSoC):
self.submodules.rtio = rtio.RTIO(rtio_channels, self.submodules.rtio = rtio.RTIO(rtio_channels,
clk_freq=125000000) clk_freq=125000000)
self.add_constant("RTIO_FINE_TS_WIDTH", self.rtio.fine_ts_width) self.add_constant("RTIO_FINE_TS_WIDTH", self.rtio.fine_ts_width)
self.add_constant("DDS_RTIO_CLK_RATIO", 8 >> self.rtio.fine_ts_width)
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels) self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
if isinstance(platform.toolchain, XilinxVivadoToolchain): if isinstance(platform.toolchain, XilinxVivadoToolchain):

1
soc/targets/artiq_pipistrello.py
View File

@ -128,6 +128,7 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
self.submodules.rtio = rtio.RTIO(rtio_channels, self.submodules.rtio = rtio.RTIO(rtio_channels,
clk_freq=125000000) clk_freq=125000000)
self.add_constant("RTIO_FINE_TS_WIDTH", self.rtio.fine_ts_width) self.add_constant("RTIO_FINE_TS_WIDTH", self.rtio.fine_ts_width)
self.add_constant("DDS_RTIO_CLK_RATIO", 8 >> self.rtio.fine_ts_width)
self.submodules.rtio_mon = rtio.MonInj(rtio_channels) self.submodules.rtio_mon = rtio.MonInj(rtio_channels)
# CPU connections # CPU connections