From 03fe71228b051a624e7429efc68f25064675dcfc Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Fri, 19 Jun 2015 11:01:43 -0600
Subject: [PATCH] dds: phase computation fixes

---
 soc/runtime/dds.c                | 24 ++++++++++++------------
 soc/targets/artiq_kc705.py       |  1 +
 soc/targets/artiq_pipistrello.py |  1 +
 3 files changed, 14 insertions(+), 12 deletions(-)

diff --git a/soc/runtime/dds.c b/soc/runtime/dds.c
index fc871fa26..5e94d5e1c 100644
--- a/soc/runtime/dds.c
+++ b/soc/runtime/dds.c
@@ -55,26 +55,26 @@ static void dds_set_one(long long int now, long long int ref_time, int channel,
 {
     DDS_WRITE(DDS_GPIO, channel);
 
-    if(phase_mode == PHASE_MODE_CONTINUOUS)
-        /* Do not clear phase accumulator on FUD */
-        DDS_WRITE(0x02, 0x00);
-    else
-        /* Clear phase accumulator on FUD */
-        DDS_WRITE(0x02, 0x40);
-
     DDS_WRITE(DDS_FTW0, ftw & 0xff);
     DDS_WRITE(DDS_FTW1, (ftw >> 8) & 0xff);
     DDS_WRITE(DDS_FTW2, (ftw >> 16) & 0xff);
     DDS_WRITE(DDS_FTW3, (ftw >> 24) & 0xff);
 
-    /* We assume that the RTIO clock is DDS SYNCLK */
-    if(phase_mode == PHASE_MODE_TRACKING)
-        pow += (ref_time >> RTIO_FINE_TS_WIDTH)*ftw >> 18;
-    if(phase_mode != PHASE_MODE_CONTINUOUS) {
+    /* We need the RTIO fine timestamp clock to be phase-locked
+     * to DDS SYNCLK, and divided by an integer DDS_RTIO_CLK_RATIO.
+     */
+    if(phase_mode == PHASE_MODE_CONTINUOUS) {
+        /* Do not clear phase accumulator on FUD */
+        DDS_WRITE(0x02, 0x00);
+    } else {
         long long int fud_time;
 
+        /* Clear phase accumulator on FUD */
+        DDS_WRITE(0x02, 0x40);
         fud_time = now + 2*DURATION_WRITE;
-        pow -= ((ref_time - fud_time) >> RTIO_FINE_TS_WIDTH)*ftw >> 18;
+        pow -= (ref_time - fud_time)*DDS_RTIO_CLK_RATIO*ftw >> 18;
+        if(phase_mode == PHASE_MODE_TRACKING)
+            pow += ref_time*DDS_RTIO_CLK_RATIO*ftw >> 18;
     }
 
     DDS_WRITE(DDS_POW0, pow & 0xff);
diff --git a/soc/targets/artiq_kc705.py b/soc/targets/artiq_kc705.py
index d45badfe7..15ce34908 100644
--- a/soc/targets/artiq_kc705.py
+++ b/soc/targets/artiq_kc705.py
@@ -93,6 +93,7 @@ class NIST_QC1(MiniSoC, AMPSoC):
         self.submodules.rtio = rtio.RTIO(rtio_channels,
                                          clk_freq=125000000)
         self.add_constant("RTIO_FINE_TS_WIDTH", self.rtio.fine_ts_width)
+        self.add_constant("DDS_RTIO_CLK_RATIO", 8 >> self.rtio.fine_ts_width)
         self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
 
         if isinstance(platform.toolchain, XilinxVivadoToolchain):
diff --git a/soc/targets/artiq_pipistrello.py b/soc/targets/artiq_pipistrello.py
index f18c7cfe0..9a149a748 100644
--- a/soc/targets/artiq_pipistrello.py
+++ b/soc/targets/artiq_pipistrello.py
@@ -128,6 +128,7 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
         self.submodules.rtio = rtio.RTIO(rtio_channels,
                                          clk_freq=125000000)
         self.add_constant("RTIO_FINE_TS_WIDTH", self.rtio.fine_ts_width)
+        self.add_constant("DDS_RTIO_CLK_RATIO", 8 >> self.rtio.fine_ts_width)
         self.submodules.rtio_mon = rtio.MonInj(rtio_channels)
 
         # CPU connections