mirror of https://github.com/m-labs/artiq.git
29 lines
1.1 KiB
Python
29 lines
1.1 KiB
Python
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from migen.fhdl.std import *
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from migen.bank.description import *
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from migen.genlib.cdc import BusSynchronizer
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class Monitor(Module, AutoCSR):
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def __init__(self, channels):
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chan_probes = [c.probes for c in channels]
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max_chan_probes = max(len(cp) for cp in chan_probes)
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max_probe_len = max(flen(p) for cp in chan_probes for p in cp)
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self.chan_sel = CSRStorage(bits_for(len(chan_probes)-1))
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self.probe_sel = CSRStorage(bits_for(max_chan_probes-1))
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self.probe_value = CSRStatus(max_probe_len)
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# # #
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chan_probes_sys = []
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for cp in chan_probes:
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cp_sys = []
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for p in cp:
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vs = BusSynchronizer(flen(p), "rio", "rsys")
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self.submodules += vs
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self.comb += vs.i.eq(p)
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cp_sys.append(vs.o)
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cp_sys += [0]*(max_chan_probes-len(cp))
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chan_probes_sys.append(Array(cp_sys)[self.probe_sel.storage])
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self.comb += self.probe_value.status.eq(
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Array(chan_probes_sys)[self.chan_sel.storage])
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