2015-12-31 21:54:54 +08:00
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import builtins
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2016-01-26 07:48:13 +08:00
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import linecache
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import re
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import os
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2016-01-26 09:04:06 +08:00
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from artiq import __artiq_dir__ as artiq_dir
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2016-01-26 06:52:52 +08:00
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from artiq.coredevice.runtime import source_loader
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2015-08-07 16:44:49 +08:00
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2015-12-22 12:03:11 +08:00
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2015-12-31 21:54:54 +08:00
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ZeroDivisionError = builtins.ZeroDivisionError
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ValueError = builtins.ValueError
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IndexError = builtins.IndexError
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2015-08-08 21:01:08 +08:00
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2015-12-22 12:03:11 +08:00
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2016-01-26 06:52:52 +08:00
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class CoreException:
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"""Information about an exception raised or passed through the core device."""
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def __init__(self, name, message, params, traceback):
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if ':' in name:
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exn_id, self.name = name.split(':', 2)
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self.id = int(exn_id)
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else:
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self.id, self.name = 0, name
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self.message, self.params = message, params
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self.traceback = list(traceback)
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def __str__(self):
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lines = []
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lines.append("Core Device Traceback (most recent call last):")
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2016-02-25 01:44:07 +08:00
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last_address = 0
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2016-01-26 06:52:52 +08:00
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for (filename, line, column, function, address) in self.traceback:
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stub_globals = {"__name__": filename, "__loader__": source_loader}
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source_line = linecache.getline(filename, line, stub_globals)
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indentation = re.search(r"^\s*", source_line).end()
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if address is None:
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formatted_address = ""
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2016-02-25 01:44:07 +08:00
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elif address == last_address:
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formatted_address = " (inlined)"
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2016-01-26 06:52:52 +08:00
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else:
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2016-04-03 01:48:09 +08:00
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formatted_address = " (RA=+0x{:x})".format(address)
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2016-02-25 01:44:07 +08:00
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last_address = address
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2016-01-26 06:52:52 +08:00
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2016-01-26 09:04:06 +08:00
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filename = filename.replace(artiq_dir, "<artiq>")
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2016-01-26 06:52:52 +08:00
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if column == -1:
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lines.append(" File \"{file}\", line {line}, in {function}{address}".
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format(file=filename, line=line, function=function,
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address=formatted_address))
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lines.append(" {}".format(source_line.strip() if source_line else "<unknown>"))
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else:
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lines.append(" File \"{file}\", line {line}, column {column},"
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" in {function}{address}".
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format(file=filename, line=line, column=column + 1,
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function=function, address=formatted_address))
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lines.append(" {}".format(source_line.strip() if source_line else "<unknown>"))
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lines.append(" {}^".format(" " * (column - indentation)))
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lines.append("{}({}): {}".format(self.name, self.id,
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self.message.format(*self.params)))
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return "\n".join(lines)
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2015-12-31 21:54:54 +08:00
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class InternalError(Exception):
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2015-08-07 16:44:49 +08:00
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"""Raised when the runtime encounters an internal error condition."""
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2016-01-19 09:45:25 +08:00
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artiq_builtin = True
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2015-08-07 16:44:49 +08:00
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2015-12-22 12:03:11 +08:00
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2016-01-10 22:43:30 +08:00
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class CacheError(Exception):
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"""Raised when putting a value into a cache row would violate memory safety."""
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2016-01-19 09:45:25 +08:00
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artiq_builtin = True
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2016-01-10 22:43:30 +08:00
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2015-12-31 21:54:54 +08:00
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class RTIOUnderflow(Exception):
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2015-08-07 16:44:49 +08:00
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"""Raised when the CPU fails to submit a RTIO event early enough
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(with respect to the event's timestamp).
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The offending event is discarded and the RTIO core keeps operating.
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"""
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2016-01-19 09:45:25 +08:00
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artiq_builtin = True
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2015-08-07 16:44:49 +08:00
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2015-12-31 21:54:54 +08:00
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class RTIOSequenceError(Exception):
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2015-08-07 16:44:49 +08:00
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"""Raised when an event is submitted on a given channel with a timestamp
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not larger than the previous one.
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The offending event is discarded and the RTIO core keeps operating.
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"""
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2016-01-19 09:45:25 +08:00
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artiq_builtin = True
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2015-08-07 16:44:49 +08:00
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2015-12-31 21:54:54 +08:00
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class RTIOOverflow(Exception):
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2015-08-07 16:44:49 +08:00
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"""Raised when at least one event could not be registered into the RTIO
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input FIFO because it was full (CPU not reading fast enough).
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This does not interrupt operations further than cancelling the current
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read attempt and discarding some events. Reading can be reattempted after
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the exception is caught, and events will be partially retrieved.
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"""
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2016-01-19 09:45:25 +08:00
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artiq_builtin = True
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2015-08-07 16:44:49 +08:00
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2017-02-26 10:50:20 +08:00
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class DMAError(Exception):
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"""Raised when performing an invalid DMA operation."""
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artiq_builtin = True
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2016-03-19 12:15:19 +08:00
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class DDSError(Exception):
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2015-08-07 16:44:49 +08:00
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"""Raised when attempting to start a DDS batch while already in a batch,
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2016-03-19 12:15:19 +08:00
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when too many commands are batched, and when DDS channel settings are
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incorrect.
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2015-08-07 16:44:49 +08:00
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"""
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2016-03-05 00:16:12 +08:00
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2016-03-19 06:29:42 +08:00
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class WatchdogExpired(Exception):
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"""Raised when a watchdog expires."""
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class ClockFailure(Exception):
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2016-03-19 18:01:00 +08:00
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"""Raised when RTIO PLL has lost lock."""
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2017-06-19 14:22:59 +08:00
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class I2CError(Exception):
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"""Raised when a I2C transaction fails."""
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pass
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class SPIError(Exception):
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2017-06-19 15:42:10 +08:00
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"""Raised when a SPI transaction fails."""
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2017-06-19 14:22:59 +08:00
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pass
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