M-Labs/artiq
2
0
Fork 2
mirror of https://github.com/m-labs/artiq.git synced 2024-12-25 03:08:27 +08:00
Code Issues Projects Releases Wiki Activity

coredevice.exceptions: add CacheError.

Browse Source
This commit is contained in:
whitequark 2016-01-10 14:43:30 +00:00
parent 211af77e77
commit 4198601abb
1 changed files with 4 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
artiq/coredevice/exceptions.py
View File

@ -11,6 +11,10 @@ class InternalError(Exception):
"""Raised when the runtime encounters an internal error condition."""
class CacheError(Exception):
"""Raised when putting a value into a cache row would violate memory safety."""
class RTIOUnderflow(Exception):
"""Raised when the CPU fails to submit a RTIO event early enough
(with respect to the event's timestamp).