mirror of https://github.com/m-labs/artiq
46 lines
1.3 KiB
Python
46 lines
1.3 KiB
Python
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from artiq.language.core import kernel, portable, delay
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from artiq.coredevice.rtio import rtio_output, rtio_input_data
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from artiq.language.units import us
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from artiq.language.types import TInt32, TList, TFloat
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PHASER_ADDR_BOARD_ID = 0x00
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PHASER_BOARD_ID = 19
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class Phaser:
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kernel_invariants = {"core", "channel_base"}
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def __init__(self, dmgr, channel_base, readback_delay=1,
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core_device="core"):
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self.channel_base = channel_base << 8
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self.core = dmgr.get(core_device)
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self.readback_delay = readback_delay
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@kernel
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def init(self):
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board_id = self.read(PHASER_ADDR_BOARD_ID)
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if board_id != PHASER_BOARD_ID:
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raise ValueError("invalid board id")
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@kernel
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def write(self, addr, data):
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"""Write data to a Fastino register.
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:param addr: Address to write to.
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:param data: Data to write.
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"""
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rtio_output(self.channel_base | addr | 0x80, data)
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@kernel
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def read(self, addr):
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"""Read from Fastino register.
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TODO: untested
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:param addr: Address to read from.
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:return: The data read.
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"""
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rtio_output(self.channel_base | addr, 0)
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response = rtio_input_data(self.channel_base >> 8)
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return response >> self.readback_delay
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