2016-01-26 07:03:01 +08:00
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from artiq.experiment import *
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2014-06-18 19:43:09 +08:00
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2014-09-05 12:03:22 +08:00
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2015-07-14 04:08:20 +08:00
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class SimpleSimulation(EnvExperiment):
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2015-03-08 22:43:04 +08:00
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"""Simple simulation"""
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2015-02-21 05:01:34 +08:00
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2015-07-14 04:08:20 +08:00
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def build(self):
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2015-10-04 00:18:21 +08:00
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self.setattr_device("core")
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2015-07-14 04:08:20 +08:00
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for wo in "abcd":
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2015-10-04 00:18:21 +08:00
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self.setattr_device(wo)
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2014-09-05 12:03:22 +08:00
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@kernel
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def run(self):
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2016-02-22 21:24:43 +08:00
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with interleave:
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2014-09-05 12:03:22 +08:00
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with sequential:
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self.a.pulse(100*MHz, 20*us)
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self.b.pulse(200*MHz, 20*us)
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with sequential:
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self.c.pulse(300*MHz, 10*us)
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self.d.pulse(400*MHz, 20*us)
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2014-06-18 19:43:09 +08:00
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2014-10-05 16:24:21 +08:00
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def main():
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2015-07-14 04:08:20 +08:00
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from artiq.sim import devices
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dmgr = dict()
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dmgr["core"] = devices.Core(dmgr)
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for wo in "abcd":
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dmgr[wo] = devices.WaveOutput(dmgr, wo)
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exp = SimpleSimulation(dmgr)
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2014-09-05 12:03:22 +08:00
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exp.run()
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2014-10-05 16:24:21 +08:00
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if __name__ == "__main__":
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main()
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