mirror of
https://github.com/m-labs/artiq.git
synced 2024-12-25 11:18:27 +08:00
Rename 'with parallel' to 'with interleave' (#265).
This commit is contained in:
parent
b0e7fddc32
commit
51a5910002
@ -144,8 +144,8 @@ def fn_print():
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def fn_kernel():
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return types.TBuiltinFunction("kernel")
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def obj_parallel():
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return types.TBuiltin("parallel")
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def obj_interleave():
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return types.TBuiltin("interleave")
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def obj_sequential():
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return types.TBuiltin("sequential")
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@ -1418,7 +1418,7 @@ class Loop(Terminator):
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def opcode(self):
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return "loop({} times)".format(self.trip_count)
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class Parallel(Terminator):
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class Interleave(Terminator):
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"""
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An instruction that schedules several threads of execution
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in parallel.
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@ -1428,7 +1428,7 @@ class Parallel(Terminator):
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super().__init__(destinations, builtins.TNone(), name)
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def opcode(self):
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return "parallel"
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return "interleave"
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def destinations(self):
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return self.operands
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@ -30,7 +30,7 @@ def globals():
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"portable": builtins.fn_kernel(),
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# ARTIQ context managers
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"parallel": builtins.obj_parallel(),
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"interleave": builtins.obj_interleave(),
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"sequential": builtins.obj_sequential(),
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"watchdog": builtins.fn_watchdog(),
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@ -747,8 +747,8 @@ class ARTIQIRGenerator(algorithm.Visitor):
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if types.is_builtin(context_expr_node.type, "sequential"):
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self.visit(node.body)
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return
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elif types.is_builtin(context_expr_node.type, "parallel"):
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parallel = self.append(ir.Parallel([]))
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elif types.is_builtin(context_expr_node.type, "interleave"):
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interleave = self.append(ir.Interleave([]))
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heads, tails = [], []
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for stmt in node.body:
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@ -758,7 +758,7 @@ class ARTIQIRGenerator(algorithm.Visitor):
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tails.append(self.current_block)
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for head in heads:
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parallel.add_destination(head)
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interleave.add_destination(head)
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self.current_block = self.add_block()
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for tail in tails:
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@ -993,7 +993,7 @@ class Inferencer(algorithm.Visitor):
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self.generic_visit(node)
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typ = node.context_expr.type
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if (types.is_builtin(typ, "parallel") or types.is_builtin(typ, "sequential") or
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if (types.is_builtin(typ, "interleave") or types.is_builtin(typ, "sequential") or
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(isinstance(node.context_expr, asttyped.CallT) and
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types.is_builtin(node.context_expr.func.type, "watchdog"))):
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# builtin context managers
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@ -1092,7 +1092,7 @@ class Inferencer(algorithm.Visitor):
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for item_node in node.items:
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typ = item_node.context_expr.type.find()
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if (types.is_builtin(typ, "parallel") or types.is_builtin(typ, "sequential")) and \
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if (types.is_builtin(typ, "interleave") or types.is_builtin(typ, "sequential")) and \
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len(node.items) != 1:
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diag = diagnostic.Diagnostic("error",
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"the '{kind}' context manager must be the only one in a 'with' statement",
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@ -66,7 +66,7 @@ class Interleaver:
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postdom_tree = None
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for insn in func.instructions():
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if not isinstance(insn, ir.Parallel):
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if not isinstance(insn, ir.Interleave):
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continue
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# Lazily compute dominators.
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@ -79,7 +79,7 @@ class Interleaver:
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source_times = [0 for _ in source_blocks]
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if len(source_blocks) == 1:
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# Immediate dominator for a parallel instruction with one successor
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# Immediate dominator for a interleave instruction with one successor
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# is the first instruction in the body of the statement which created
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# it, but below we expect that it would be the first instruction after
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# the statement itself.
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@ -87,7 +87,7 @@ class Interleaver:
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continue
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interleave_until = postdom_tree.immediate_dominator(insn.basic_block)
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assert interleave_until is not None # no nonlocal flow in `with parallel`
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assert interleave_until is not None # no nonlocal flow in `with interleave`
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assert interleave_until not in source_blocks
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while len(source_blocks) > 0:
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@ -111,7 +111,7 @@ class Interleaver:
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assert target_time_delta >= 0
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target_terminator = target_block.terminator()
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if isinstance(target_terminator, ir.Parallel):
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if isinstance(target_terminator, ir.Interleave):
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target_terminator.replace_with(ir.Branch(source_block))
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elif isinstance(target_terminator, (ir.Delay, ir.Branch)):
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target_terminator.set_target(source_block)
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@ -119,7 +119,7 @@ class Interleaver:
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assert False
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source_terminator = source_block.terminator()
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if isinstance(source_terminator, ir.Parallel):
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if isinstance(source_terminator, ir.Interleave):
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source_terminator.replace_with(ir.Branch(source_terminator.target()))
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elif isinstance(source_terminator, ir.Branch):
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pass
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@ -149,7 +149,7 @@ class Interleaver:
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if old_decomp.static_target_function is None:
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diag = diagnostic.Diagnostic("fatal",
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"it is not possible to interleave this function call within "
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"a 'with parallel:' statement because the compiler could not "
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"a 'with interleave:' statement because the compiler could not "
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"prove that the same function would always be called", {},
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old_decomp.loc)
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self.engine.process(diag)
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@ -219,7 +219,7 @@ class IODelayEstimator(algorithm.Visitor):
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self.visit(node.items)
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context_expr = node.items[0].context_expr
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if len(node.items) == 1 and types.is_builtin(context_expr.type, "parallel"):
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if len(node.items) == 1 and types.is_builtin(context_expr.type, "interleave"):
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try:
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delays = []
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for stmt in node.body:
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@ -235,7 +235,7 @@ class IODelayEstimator(algorithm.Visitor):
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# since there's no chance that the code will never actually execute
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# inside a `with` statement after all.
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note = diagnostic.Diagnostic("note",
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"while interleaving this 'with parallel:' statement", {},
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"while interleaving this 'with interleave:' statement", {},
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node.loc)
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error.cause.notes += [note]
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self.engine.process(error.cause)
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@ -249,11 +249,11 @@ class IODelayEstimator(algorithm.Visitor):
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if flow_stmt is not None:
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note = diagnostic.Diagnostic("note",
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"this '{kind}' statement transfers control out of "
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"the 'with parallel:' statement",
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"the 'with interleave:' statement",
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{"kind": flow_stmt.keyword_loc.source()},
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flow_stmt.loc)
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diag = diagnostic.Diagnostic("error",
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"cannot interleave this 'with parallel:' statement", {},
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"cannot interleave this 'with interleave:' statement", {},
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node.keyword_loc.join(node.colon_loc), notes=[note])
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self.engine.process(diag)
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@ -13,7 +13,7 @@ __all__ = ["host_int", "int", "host_round", "round",
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# global namespace for kernels
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kernel_globals = (
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"sequential", "parallel",
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"sequential", "parallel", "interleave",
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"delay_mu", "now_mu", "at_mu", "delay",
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"seconds_to_mu", "mu_to_seconds",
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"watchdog"
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@ -264,7 +264,7 @@ _time_manager = _DummyTimeManager()
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def set_time_manager(time_manager):
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"""Set the time manager used for simulating kernels by running them
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directly inside the Python interpreter. The time manager responds to the
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entering and leaving of parallel/sequential blocks, delays, etc. and
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entering and leaving of interleave/parallel/sequential blocks, delays, etc. and
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provides a time-stamped logging facility for events.
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"""
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global _time_manager
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@ -288,7 +288,7 @@ class _Parallel:
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The execution time of a parallel block is the execution time of its longest
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statement. A parallel block may contain sequential blocks, which themselves
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may contain parallel blocks, etc.
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may contain interleave blocks, etc.
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"""
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def __enter__(self):
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_time_manager.enter_parallel()
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@ -296,7 +296,7 @@ class _Parallel:
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def __exit__(self, type, value, traceback):
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_time_manager.exit()
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parallel = _Parallel()
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interleave = _Parallel() # no difference in semantics on host
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def delay_mu(duration):
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"""Increases the RTIO time by the given amount (in machine units)."""
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@ -12,7 +12,7 @@ class CreateTTLPulse(EnvExperiment):
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def run(self):
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self.ttl_inout.output()
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delay_mu(100)
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with parallel:
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with interleave:
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self.ttl_inout.gate_both_mu(1200)
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with sequential:
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delay_mu(100)
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@ -100,7 +100,7 @@ class _Pulses(EnvExperiment):
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@kernel
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def run(self):
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for i in range(3):
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with parallel:
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with interleave:
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with sequential:
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self.a.pulse(100+i, 20*us)
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self.b.pulse(200+i, 20*us)
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@ -16,7 +16,7 @@ class RTT(EnvExperiment):
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def run(self):
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self.ttl_inout.output()
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delay(1*us)
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with parallel:
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with interleave:
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# make sure not to send two commands into the same RTIO
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# channel with the same timestamp
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self.ttl_inout.gate_rising(5*us)
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@ -37,7 +37,7 @@ class Loopback(EnvExperiment):
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def run(self):
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self.loop_in.input()
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delay(1*us)
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with parallel:
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with interleave:
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self.loop_in.gate_rising(2*us)
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with sequential:
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delay(1*us)
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@ -57,7 +57,7 @@ class ClockGeneratorLoopback(EnvExperiment):
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self.loop_clock_in.input()
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self.loop_clock_out.stop()
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delay(1*us)
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with parallel:
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with interleave:
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self.loop_clock_in.gate_rising(10*us)
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with sequential:
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delay(200*ns)
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@ -110,7 +110,7 @@ class LoopbackCount(EnvExperiment):
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def run(self):
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self.ttl_inout.output()
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delay(5*us)
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with parallel:
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with interleave:
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self.ttl_inout.gate_rising(10*us)
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with sequential:
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for i in range(self.npulses):
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@ -1,6 +1,6 @@
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# RUN: %python -m artiq.compiler.testbench.inferencer +diag %s >%t
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# RUN: OutputCheck %s --file-to-check=%t
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# CHECK-L: ${LINE:+1}: error: the 'parallel' context manager must be the only one in a 'with' statement
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with parallel, sequential:
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# CHECK-L: ${LINE:+1}: error: the 'interleave' context manager must be the only one in a 'with' statement
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with interleave, sequential:
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pass
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@ -2,4 +2,4 @@
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# RUN: OutputCheck %s --file-to-check=%t
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# CHECK-L: as x:NoneType
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with parallel as x: pass
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with interleave as x: pass
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@ -2,7 +2,7 @@
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# RUN: OutputCheck %s --file-to-check=%t
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def f():
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with parallel:
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with interleave:
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if True:
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print(1)
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else:
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@ -10,7 +10,7 @@ def g():
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x = f if True else g
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def h():
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with parallel:
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with interleave:
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f()
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# CHECK-L: ${LINE:+1}: fatal: it is not possible to interleave this function call within a 'with parallel:' statement because the compiler could not prove that the same function would always be called
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# CHECK-L: ${LINE:+1}: fatal: it is not possible to interleave this function call within a 'with interleave:' statement because the compiler could not prove that the same function would always be called
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x()
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@ -2,16 +2,16 @@
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# RUN: OutputCheck %s --file-to-check=%t
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def f():
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# CHECK-L: ${LINE:+1}: error: cannot interleave this 'with parallel:' statement
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with parallel:
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# CHECK-L: ${LINE:+1}: note: this 'return' statement transfers control out of the 'with parallel:' statement
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# CHECK-L: ${LINE:+1}: error: cannot interleave this 'with interleave:' statement
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with interleave:
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# CHECK-L: ${LINE:+1}: note: this 'return' statement transfers control out of the 'with interleave:' statement
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return
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delay(1.0)
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def g():
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while True:
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# CHECK-L: ${LINE:+1}: error: cannot interleave this 'with parallel:' statement
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with parallel:
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# CHECK-L: ${LINE:+1}: note: this 'break' statement transfers control out of the 'with parallel:' statement
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# CHECK-L: ${LINE:+1}: error: cannot interleave this 'with interleave:' statement
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with interleave:
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# CHECK-L: ${LINE:+1}: note: this 'break' statement transfers control out of the 'with interleave:' statement
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break
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delay(1.0)
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@ -5,7 +5,7 @@ def f():
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delay_mu(2)
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def g():
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with parallel:
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with interleave:
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with sequential:
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print("A", now_mu())
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f()
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@ -5,7 +5,7 @@ def f(n):
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delay_mu(n)
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def g():
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with parallel:
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with interleave:
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with sequential:
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print("A", now_mu())
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f(2)
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@ -2,7 +2,7 @@
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# RUN: OutputCheck %s --file-to-check=%t
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def g():
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with parallel:
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with interleave:
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with sequential:
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print("A", now_mu())
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delay_mu(2)
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@ -2,7 +2,7 @@
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# RUN: OutputCheck %s --file-to-check=%t
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def g():
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with parallel:
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with interleave:
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with sequential:
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print("A", now_mu())
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delay_mu(3)
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@ -5,7 +5,7 @@ def f():
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delay_mu(2)
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def g():
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with parallel:
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with interleave:
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f()
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delay_mu(2)
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print(now_mu())
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@ -1,7 +1,7 @@
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# RUN: %python -m artiq.compiler.testbench.jit %s >%t
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# RUN: OutputCheck %s --file-to-check=%t
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with parallel:
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with interleave:
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for x in range(10):
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delay_mu(1)
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print("a", x)
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@ -2,7 +2,7 @@
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# RUN: OutputCheck %s --file-to-check=%t
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def f():
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with parallel:
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with interleave:
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# CHECK-L: ${LINE:+1}: error: while statement cannot be interleaved
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while True:
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delay_mu(1)
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@ -3,13 +3,13 @@
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# CHECK-L: f: (a:int(width=64), b:int(width=64))->NoneType delay(max(a, b) mu)
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def f(a, b):
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with parallel:
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with interleave:
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delay_mu(a)
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delay_mu(b)
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# CHECK-L: g: (a:int(width=64))->NoneType delay(max(a, 200) mu)
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def g(a):
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with parallel:
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with interleave:
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delay_mu(100)
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delay_mu(200)
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delay_mu(a)
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@ -1,6 +1,6 @@
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# RUN: %python -m artiq.compiler.testbench.signature %s >%t
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with parallel:
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with interleave:
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delay(1.0)
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t0 = now_mu()
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print(t0)
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@ -156,23 +156,23 @@ The core device records the real-time IO waveforms into a circular buffer. It is
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Afterwards, the recorded data can be extracted and written to a VCD file using ``artiq_coreanalyzer -w rtio.vcd`` (see: :ref:`core-device-rtio-analyzer-tool`). VCD files can be viewed using third-party tools such as GtkWave.
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Parallel and sequential blocks
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------------------------------
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Interleave and sequential blocks
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--------------------------------
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It is often necessary that several pulses overlap one another. This can be expressed through the use of ``with parallel`` constructs, in which all statements execute at the same time. The execution time of the ``parallel`` block is the execution time of its longest statement.
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It is often necessary that several pulses overlap one another. This can be expressed through the use of ``with interleave`` constructs, in which all statements execute at the same time. The execution time of the ``interleave`` block is the execution time of its longest statement.
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Try the following code and observe the generated pulses on a 2-channel oscilloscope or logic analyzer: ::
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for i in range(1000000):
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with parallel:
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with interleave:
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self.ttl0.pulse(2*us)
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self.ttl1.pulse(4*us)
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delay(4*us)
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Within a parallel block, some statements can be made sequential again using a ``with sequential`` construct. Observe the pulses generated by this code: ::
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Within a interleave block, some statements can be made sequential again using a ``with sequential`` construct. Observe the pulses generated by this code: ::
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for i in range(1000000):
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with parallel:
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with interleave:
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with sequential:
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self.ttl0.pulse(2*us)
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delay(1*us)
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@ -181,4 +181,4 @@ Within a parallel block, some statements can be made sequential again using a ``
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delay(4*us)
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.. warning::
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In its current implementation, ARTIQ only supports those pulse sequences that can be interleaved at compile time into a sequential series of on/off events. Combinations of ``parallel``/``sequential`` blocks that require multithreading (due to the parallel execution of long loops, complex algorithms, or algorithms that depend on external input) will cause the compiler to return an error.
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In its current implementation, ARTIQ only supports those pulse sequences that can be interleaved at compile time into a sequential series of on/off events. Combinations of ``interleave``/``sequential`` blocks that require multithreading (due to the parallel execution of long loops, complex algorithms, or algorithms that depend on external input) will cause the compiler to return an error.
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|
@ -117,10 +117,10 @@ dds.pulse(200*MHz, 11*us) # exactly 1 ms after trigger
|
||||
\footnotesize
|
||||
\begin{minted}[frame=leftline]{python}
|
||||
with sequential:
|
||||
with parallel:
|
||||
with interleave:
|
||||
a.pulse(100*MHz, 10*us)
|
||||
b.pulse(200*MHz, 20*us)
|
||||
with parallel:
|
||||
with interleave:
|
||||
c.pulse(300*MHz, 30*us)
|
||||
d.pulse(400*MHz, 20*us)
|
||||
\end{minted}
|
||||
@ -128,7 +128,7 @@ with sequential:
|
||||
\begin{itemize}
|
||||
\item Experiments are inherently parallel:
|
||||
simultaneous laser pulses, parallel cooling of ions in different trap zones
|
||||
\item \verb!parallel! and \verb!sequential! contexts with arbitrary nesting
|
||||
\item \verb!interleave! and \verb!sequential! contexts with arbitrary nesting
|
||||
\item \verb!a! and \verb!b! pulses both start at the same time
|
||||
\item \verb!c! and \verb!d! pulses both start when \verb!a! and \verb!b! are both done
|
||||
(after 20\,µs)
|
||||
@ -181,7 +181,7 @@ class Experiment:
|
||||
|
||||
@kernel
|
||||
def run(self):
|
||||
with parallel:
|
||||
with interleave:
|
||||
self.ion1.cool(duration=10*us)
|
||||
self.ion2.cool(frequency=...)
|
||||
self.transporter.move(speed=...)
|
||||
@ -222,7 +222,7 @@ class Experiment:
|
||||
\item RPC and exception mappings are generated
|
||||
\item Constants and small kernels are inlined
|
||||
\item Small loops are unrolled
|
||||
\item Statements in parallel blocks are interleaved
|
||||
\item Statements in interleave blocks are interleaved
|
||||
\item Time is converted to RTIO clock cycles
|
||||
\item The Python AST is converted to LLVM IR
|
||||
\item The LLVM IR is compiled to OpenRISC machine code
|
||||
@ -244,7 +244,7 @@ class Experiment:
|
||||
\item Scheduling of experiments \\
|
||||
e.g.\ calibrations, queue
|
||||
\item Archival of results (HDF5 format)
|
||||
\item Graphical user interface \\
|
||||
\item Graphical user interface \\
|
||||
run with arguments, schedule, real-time plotting
|
||||
\end{itemize}
|
||||
\end{frame}
|
||||
@ -262,7 +262,7 @@ class Experiment:
|
||||
\item Novatech 409B DDS
|
||||
\item Thorlabs motor controllers
|
||||
\end{itemize}
|
||||
\end{frame}
|
||||
\end{frame}
|
||||
|
||||
\begin{frame}
|
||||
\begin{center}
|
||||
|
@ -10,7 +10,7 @@
|
||||
\usepackage{multimedia}
|
||||
\usepackage{tikz}
|
||||
\usetikzlibrary{arrows,shapes,snakes,positioning,backgrounds,decorations,graphs}
|
||||
\definecolor{ethblue}{rgb}{0, 0.2, 0.3568}
|
||||
\definecolor{ethblue}{rgb}{0, 0.2, 0.3568}
|
||||
\usepackage{minted}
|
||||
|
||||
\mode<presentation>
|
||||
@ -133,10 +133,10 @@ dds.pulse(200*MHz, 11*us) # exactly 1 ms after trigger
|
||||
\footnotesize
|
||||
\begin{minted}[frame=leftline]{python}
|
||||
with sequential:
|
||||
with parallel:
|
||||
with interleave:
|
||||
a.pulse(100*MHz, 10*us)
|
||||
b.pulse(200*MHz, 20*us)
|
||||
with parallel:
|
||||
with interleave:
|
||||
c.pulse(300*MHz, 30*us)
|
||||
d.pulse(400*MHz, 20*us)
|
||||
\end{minted}
|
||||
@ -144,7 +144,7 @@ with sequential:
|
||||
\begin{itemize}
|
||||
\item Experiments are inherently parallel:
|
||||
simultaneous laser pulses, parallel cooling of ions in different trap zones
|
||||
\item \verb!parallel! and \verb!sequential! contexts with arbitrary nesting
|
||||
\item \verb!interleave! and \verb!sequential! contexts with arbitrary nesting
|
||||
\item \verb!a! and \verb!b! pulses both start at the same time
|
||||
\item \verb!c! and \verb!d! pulses both start when \verb!a! and \verb!b! are both done
|
||||
(after 20\,µs)
|
||||
@ -197,7 +197,7 @@ class Experiment:
|
||||
|
||||
@kernel
|
||||
def run(self):
|
||||
with parallel:
|
||||
with interleave:
|
||||
self.ion1.cool(duration=10*us)
|
||||
self.ion2.cool(frequency=...)
|
||||
self.transporter.move(speed=...)
|
||||
@ -238,7 +238,7 @@ class Experiment:
|
||||
\item RPC and exception mappings are generated
|
||||
\item Constants and small kernels are inlined
|
||||
\item Small loops are unrolled
|
||||
\item Statements in parallel blocks are interleaved
|
||||
\item Statements in interleave blocks are interleaved
|
||||
\item Time is converted to RTIO clock cycles
|
||||
\item The Python AST is converted to LLVM IR
|
||||
\item The LLVM IR is compiled to OpenRISC machine code
|
||||
|
@ -28,7 +28,7 @@ class PhotonHistogram(EnvExperiment):
|
||||
|
||||
@kernel
|
||||
def cool_detect(self):
|
||||
with parallel:
|
||||
with interleave:
|
||||
self.bd_sw.pulse(1*ms)
|
||||
self.bdd_sw.pulse(1*ms)
|
||||
|
||||
@ -36,7 +36,7 @@ class PhotonHistogram(EnvExperiment):
|
||||
self.bd_sw.pulse(100*us)
|
||||
|
||||
self.bd_dds.set(self.detect_f)
|
||||
with parallel:
|
||||
with interleave:
|
||||
self.bd_sw.pulse(self.detect_t)
|
||||
self.pmt.gate_rising(self.detect_t)
|
||||
|
||||
|
@ -27,7 +27,7 @@ class DDSTest(EnvExperiment):
|
||||
self.led.on()
|
||||
else:
|
||||
self.led.off()
|
||||
with parallel:
|
||||
with interleave:
|
||||
with sequential:
|
||||
self.dds0.set(100*MHz + 4*i*kHz)
|
||||
self.ttl0.pulse(500*us)
|
||||
|
@ -62,7 +62,7 @@ class TDR(EnvExperiment):
|
||||
@kernel
|
||||
def one(self, t, p):
|
||||
t0 = now_mu()
|
||||
with parallel:
|
||||
with interleave:
|
||||
self.pmt0.gate_both_mu(2*p)
|
||||
self.ttl2.pulse_mu(p)
|
||||
for i in range(len(t)):
|
||||
|
@ -24,7 +24,7 @@ class AluminumSpectroscopy(EnvExperiment):
|
||||
delay(10*us)
|
||||
self.laser_cooling.pulse(100*MHz, 100*us)
|
||||
delay(5*us)
|
||||
with parallel:
|
||||
with interleave:
|
||||
self.spectroscopy.pulse(self.spectroscopy_freq, 100*us)
|
||||
with sequential:
|
||||
delay(50*us)
|
||||
@ -32,7 +32,7 @@ class AluminumSpectroscopy(EnvExperiment):
|
||||
delay(5*us)
|
||||
while True:
|
||||
delay(5*us)
|
||||
with parallel:
|
||||
with interleave:
|
||||
self.state_detection.pulse(100*MHz, 10*us)
|
||||
photon_count = self.pmt.count_gate(10*us)
|
||||
if (photon_count < self.photon_limit_low
|
||||
|
@ -11,7 +11,7 @@ class SimpleSimulation(EnvExperiment):
|
||||
|
||||
@kernel
|
||||
def run(self):
|
||||
with parallel:
|
||||
with interleave:
|
||||
with sequential:
|
||||
self.a.pulse(100*MHz, 20*us)
|
||||
self.b.pulse(200*MHz, 20*us)
|
||||
|
Loading…
Reference in New Issue
Block a user