artiq-zynq/src/gateware
linuswck 8fd1306145 zynq_clocking: Add sys5x, 208MHz CLK & IDELAYCTRL
- Port from artiq repo
- Generate sys5x for for EEM Serdes, 208MHz REF Clock for IDELAYCTRL
- Add IDELAYCTRL for IDEALYE2 in EEM Serdes
2023-10-10 11:21:34 +08:00
..
acpki.py acpki: working 2020-09-09 21:24:49 +08:00
analyzer.py analyzer: report AXI bus errors 2020-07-20 19:51:22 +08:00
config.py refactor `write_rustc_cfg_file()` 2023-09-11 11:48:19 +08:00
dma.py dma: report AXI bus error 2020-07-21 12:47:20 +08:00
drtio_aux_controller.py gateware: add DRTIO 2021-10-08 16:12:30 +08:00
endianness.py dma: fix endianness issues 2020-07-16 17:27:08 +08:00
kasli_soc.py satellite gateware: add kernel rtio to cri 2023-10-09 11:36:23 +08:00
test_dma.py RTIO/SYS Clock merge 2023-02-17 15:52:43 +08:00
zc706.py satellite gateware: add kernel rtio to cri 2023-10-09 11:36:23 +08:00
zynq_clocking.py zynq_clocking: Add sys5x, 208MHz CLK & IDELAYCTRL 2023-10-10 11:21:34 +08:00