155 lines
5.0 KiB
Python
155 lines
5.0 KiB
Python
from migen import *
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from migen.genlib.cdc import MultiReg
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from misoc.interconnect.csr import *
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class ClockSwitchFSM(Module):
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def __init__(self):
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self.i_clk_sw = Signal()
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self.o_clk_sw = Signal()
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self.o_reset = Signal()
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###
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i_switch = Signal()
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o_switch = Signal()
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reset = Signal()
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# at 125MHz bootstrap cd, will get around 0.5ms
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delay_counter = Signal(16, reset=0xFFFF)
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# register to prevent glitches
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self.sync.bootstrap += [
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self.o_clk_sw.eq(o_switch),
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self.o_reset.eq(reset),
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]
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self.o_clk_sw.attr.add("no_retiming")
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self.o_reset.attr.add("no_retiming")
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self.i_clk_sw.attr.add("no_retiming")
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i_switch.attr.add("no_retiming")
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self.specials += MultiReg(self.i_clk_sw, i_switch, "bootstrap")
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fsm = ClockDomainsRenamer("bootstrap")(FSM(reset_state="START"))
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self.submodules += fsm
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fsm.act("START",
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If(i_switch & ~o_switch,
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NextState("RESET_START"))
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)
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fsm.act("RESET_START",
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reset.eq(1),
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If(delay_counter == 0,
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NextValue(delay_counter, 0xFFFF),
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NextState("CLOCK_SWITCH")
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).Else(
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NextValue(delay_counter, delay_counter-1),
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)
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)
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fsm.act("CLOCK_SWITCH",
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reset.eq(1),
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NextValue(o_switch, 1),
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NextValue(delay_counter, delay_counter-1),
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If(delay_counter == 0,
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NextState("END"))
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)
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fsm.act("END",
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NextValue(o_switch, 1),
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reset.eq(0))
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class SYSCRG(Module, AutoCSR):
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def __init__(self, platform, ps7, main_clk, clk_sw=None, clk_sw_status=None, freq=125e6, ext_async_rst=None, ):
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# assumes bootstrap clock is same freq as main and sys output
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys5x = ClockDomain(reset_less=True)
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self.clock_domains.cd_clk200 = ClockDomain()
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self.current_clock = CSRStatus()
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self.cd_sys.clk.attr.add("keep")
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bootstrap_clk = ClockSignal("bootstrap")
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period = 1e9/freq
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self.submodules.clk_sw_fsm = ClockSwitchFSM()
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if clk_sw is None:
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self.clock_switch = CSRStorage()
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self.comb += self.clk_sw_fsm.i_clk_sw.eq(self.clock_switch.storage)
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else:
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self.comb += self.clk_sw_fsm.i_clk_sw.eq(clk_sw)
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self.mmcm_locked = Signal()
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mmcm_sys = Signal()
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mmcm_sys4x = Signal()
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mmcm_sys5x = Signal()
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mmcm_clk208 = Signal()
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mmcm_fb_clk = Signal()
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self.specials += [
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Instance("MMCME2_ADV",
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p_STARTUP_WAIT="FALSE", o_LOCKED=self.mmcm_locked,
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p_BANDWIDTH="HIGH",
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p_REF_JITTER1=0.001,
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p_CLKIN1_PERIOD=period, i_CLKIN1=main_clk,
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p_CLKIN2_PERIOD=period, i_CLKIN2=bootstrap_clk,
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i_CLKINSEL=self.clk_sw_fsm.o_clk_sw,
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# VCO @ 1.25GHz
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p_CLKFBOUT_MULT_F=10, p_DIVCLK_DIVIDE=1,
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i_CLKFBIN=mmcm_fb_clk,
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i_RST=self.clk_sw_fsm.o_reset,
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o_CLKFBOUT=mmcm_fb_clk,
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p_CLKOUT0_DIVIDE_F=2.5, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=mmcm_sys4x,
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# 125MHz
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p_CLKOUT1_DIVIDE=10, p_CLKOUT1_PHASE=0.0, o_CLKOUT1=mmcm_sys,
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# 625MHz
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p_CLKOUT2_DIVIDE=2, p_CLKOUT2_PHASE=0.0, o_CLKOUT2=mmcm_sys5x,
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# 208MHz
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p_CLKOUT3_DIVIDE=6, p_CLKOUT3_PHASE=0.0, o_CLKOUT3=mmcm_clk208,
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),
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Instance("BUFG", i_I=mmcm_sys5x, o_O=self.cd_sys5x.clk),
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Instance("BUFG", i_I=mmcm_sys, o_O=self.cd_sys.clk),
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Instance("BUFG", i_I=mmcm_sys4x, o_O=self.cd_sys4x.clk),
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Instance("BUFG", i_I=mmcm_clk208, o_O=self.cd_clk200.clk),
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]
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if ext_async_rst is not None:
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self.specials += [
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AsyncResetSynchronizer(self.cd_sys, ~self.mmcm_locked | ext_async_rst),
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AsyncResetSynchronizer(self.cd_clk200, ~self.mmcm_locked | ext_async_rst),
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]
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else:
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self.specials += [
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AsyncResetSynchronizer(self.cd_sys, ~self.mmcm_locked),
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AsyncResetSynchronizer(self.cd_clk200, ~self.mmcm_locked),
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]
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reset_counter = Signal(4, reset=15)
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ic_reset = Signal(reset=1)
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self.sync.clk200 += \
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If(reset_counter != 0,
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reset_counter.eq(reset_counter - 1)
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).Else(
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ic_reset.eq(0)
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)
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self.specials += Instance("IDELAYCTRL", i_REFCLK=ClockSignal("clk200"), i_RST=ic_reset)
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if clk_sw_status is None:
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self.comb += self.current_clock.status.eq(self.clk_sw_fsm.o_clk_sw)
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else:
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self.comb += self.current_clock.status.eq(clk_sw_status)
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