L2 cache #95
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Reference: M-Labs/artiq-zynq#95
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Delete Branch "pca006132/artiq-zynq:l2-cache"
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Enabled L2 cache, changed optimization options, and some fixes for core1.
Passed all tests in
artiq/artiq/test/coredevice/
except RTIOtest_loopback_gate_timing
andtest_pulse_rate
which the current master also failed.Performance number (would fix some of them later):