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artiq-zynq
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ebaz4205-hydra #330

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sb10q merged 4 commits from newell/artiq-zynq:ebaz4205-hydra into master 2024-10-08 11:35:31 +08:00
Conversation 1 Commits 4 Files Changed 2 +26 -3
2 changed files with 26 additions and 3 deletions
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3
flake.nix
View File

@ -364,7 +364,8 @@
(board-package-set { target = "zc706"; variant = "acpki_nist_qc2_satellite_100mhz"; }) // (board-package-set { target = "zc706"; variant = "acpki_nist_qc2_satellite_100mhz"; }) //
(board-package-set { target = "kasli_soc"; variant = "demo"; json = ./demo.json; }) // (board-package-set { target = "kasli_soc"; variant = "demo"; json = ./demo.json; }) //
(board-package-set { target = "kasli_soc"; variant = "master"; json = ./kasli-soc-master.json; }) // (board-package-set { target = "kasli_soc"; variant = "master"; json = ./kasli-soc-master.json; }) //
(board-package-set { target = "kasli_soc"; variant = "satellite"; json = ./kasli-soc-satellite.json; }); (board-package-set { target = "kasli_soc"; variant = "satellite"; json = ./kasli-soc-satellite.json; }) //
(board-package-set { target = "ebaz4205"; variant = "base"; });
hydraJobs = packages.x86_64-linux // { inherit zc706-hitl-tests; inherit gateware-sim; inherit fmt-check; }; hydraJobs = packages.x86_64-linux // { inherit zc706-hitl-tests; inherit gateware-sim; inherit fmt-check; };

26
src/gateware/ebaz4205.py
View File

@ -212,6 +212,14 @@ class EBAZ4205(SoCCore):
self.csr_devices.append("rtio_analyzer") self.csr_devices.append("rtio_analyzer")
class BASE(EBAZ4205):
def __init__(self, rtio_clk, acpki):
EBAZ4205.__init__(self, rtio_clk, acpki)
VARIANTS = {cls.__name__.lower(): cls for cls in [BASE]}
def main(): def main():
parser = argparse.ArgumentParser( parser = argparse.ArgumentParser(
description="ARTIQ port to the EBAZ4205 control card of Ebit E9+ BTC miner" description="ARTIQ port to the EBAZ4205 control card of Ebit E9+ BTC miner"
@ -232,11 +240,25 @@ def main():
) )
parser.add_argument("--rtio-clk", default=125e6, help="RTIO Clock Frequency (Hz)") parser.add_argument("--rtio-clk", default=125e6, help="RTIO Clock Frequency (Hz)")
parser.add_argument( parser.add_argument(
"--acpki", default=False, action="store_true", help="enable ACPKI" "-V",
"--variant",
default="base",
help="variant: " "[acpki_]base" "(default: %(default)s)",
) )
args = parser.parse_args() args = parser.parse_args()
soc = EBAZ4205(rtio_clk=int(args.rtio_clk), acpki=args.acpki) rtio_clk = int(args.rtio_clk)
variant = args.variant.lower()
acpki = variant.startswith("acpki_")
if acpki:
variant = variant[6:]
try:
cls = VARIANTS[variant]
except KeyError:
raise SystemExit("Invalid variant (-V/--variant)")
soc = cls(rtio_clk=rtio_clk, acpki=acpki)
soc.finalize() soc.finalize()
if args.r is not None: if args.r is not None: