Add ebaz4205 support #327
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@ -73,9 +73,19 @@ _ddr = [
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)
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]
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# Connector J3
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_i2c = [
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(
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"i2c",
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0,
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Subsignal("scl", Pins("U12"), IOStandard("LVCMOS33")),
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Subsignal("sda", Pins("V13"), IOStandard("LVCMOS33")),
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)
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]
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class EBAZ4205(SoCCore):
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def __init__(self, rtio_clk=100e6, acpki=False):
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def __init__(self, rtio_clk=125e6, acpki=False):
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self.acpki = acpki
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platform = ebaz4205.Platform()
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@ -86,6 +96,7 @@ class EBAZ4205(SoCCore):
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)
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platform.add_extension(_ps)
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platform.add_extension(_ddr)
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platform.add_extension(_i2c)
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gmii = platform.request("gmii")
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platform.add_period_constraint(gmii.rx_clk, 10)
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@ -97,12 +108,7 @@ class EBAZ4205(SoCCore):
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ident = self.__class__.__name__
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if self.acpki:
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ident = "acpki_" + ident
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SoCCore.__init__(
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self,
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platform=platform,
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csr_data_width=32,
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ident=ident,
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)
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SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident)
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fix_serdes_timing_path(platform)
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self.config["RTIO_FREQUENCY"] = str(rtio_clk / 1e6)
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platform.add_period_constraint(self.ps7.cd_sys.clk, 10)
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@ -128,21 +134,34 @@ class EBAZ4205(SoCCore):
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# MDIO
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mdio = platform.request("mdio")
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self.comb += [
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mdio.mdc.eq(self.ps7.enet0.enet.mdio.mdc),
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]
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mdio_t = Signal()
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self.comb += mdio_t.eq(~self.ps7.enet0.enet.mdio.t_n)
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self.specials += [
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Instance(
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self.comb += mdio.mdc.eq(self.ps7.enet0.enet.mdio.mdc)
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self.specials += Instance(
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"IOBUF",
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i_I=self.ps7.enet0.enet.mdio.o,
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io_IO=mdio.mdio,
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o_O=self.ps7.enet0.enet.mdio.i,
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i_T=mdio_t,
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i_T=~self.ps7.enet0.enet.mdio.t_n,
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)
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# I2C
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i2c = self.platform.request("i2c")
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self.specials += [
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# SCL
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Instance(
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"IOBUF",
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i_I=self.ps7.i2c0.scl.o,
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io_IO=i2c.scl,
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o_O=self.ps7.i2c0.scl.i,
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i_T=~self.ps7.i2c0.scl.t_n,
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),
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# SDA
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Instance(
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"IOBUF",
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i_I=self.ps7.i2c0.sda.o,
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io_IO=i2c.sda,
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o_O=self.ps7.i2c0.sda.i,
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i_T=~self.ps7.i2c0.sda.t_n,
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),
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]
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self.rtio_channels = []
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@ -211,7 +230,7 @@ def main():
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parser.add_argument(
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"-g", default=None, help="build gateware into the specified directory"
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)
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parser.add_argument("--rtio_clk", default=100e6, help="RTIO Clock Frequency (Hz)")
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parser.add_argument("--rtio-clk", default=125e6, help="RTIO Clock Frequency (Hz)")
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parser.add_argument(
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"--acpki", default=False, action="store_true", help="enable ACPKI"
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)
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|
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@ -11,9 +11,7 @@ use super::{cache,
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core1::rtio_get_destination_status,
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dma, linalg,
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rpc::{rpc_recv, rpc_send, rpc_send_async}};
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use crate::{eh_artiq, rtio};
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#[cfg(not(feature = "target_ebaz4205"))]
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use crate::i2c;
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use crate::{eh_artiq, i2c, rtio};
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extern "C" {
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fn vsnprintf_(buffer: *mut c_char, count: size_t, format: *const c_char, va: VaList) -> c_int;
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@ -111,17 +109,11 @@ pub fn resolve(required: &[u8]) -> Option<u32> {
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api!(cache_put = cache::put),
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// i2c
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#[cfg(not(feature = "target_ebaz4205"))]
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api!(i2c_start = i2c::start),
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#[cfg(not(feature = "target_ebaz4205"))]
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api!(i2c_restart = i2c::restart),
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#[cfg(not(feature = "target_ebaz4205"))]
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api!(i2c_stop = i2c::stop),
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#[cfg(not(feature = "target_ebaz4205"))]
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api!(i2c_write = i2c::write),
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#[cfg(not(feature = "target_ebaz4205"))]
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api!(i2c_read = i2c::read),
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#[cfg(not(feature = "target_ebaz4205"))]
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api!(i2c_switch_select = i2c::switch_select),
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// subkernel
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|
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@ -21,7 +21,6 @@ pub use pl::csr::rtio_core;
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use void::Void;
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pub mod eh_artiq;
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#[cfg(not(feature = "target_ebaz4205"))]
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pub mod i2c;
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pub mod irq;
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pub mod kernel;
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|
|
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@ -100,7 +100,6 @@ pub fn main_core0() {
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info!("gateware ident: {}", identifier_read(&mut [0; 64]));
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#[cfg(not(feature = "target_ebaz4205"))]
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ksupport::i2c::init();
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#[cfg(feature = "target_kasli_soc")]
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{
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|
|
|
@ -1,6 +1,8 @@
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#[cfg(not(feature = "target_ebaz4205"))]
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use embedded_hal::blocking::delay::DelayMs;
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#[cfg(has_si5324)]
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use ksupport::i2c;
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#[cfg(not(feature = "target_ebaz4205"))]
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use libboard_artiq::pl;
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#[cfg(has_si5324)]
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use libboard_artiq::si5324;
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|
@ -10,7 +12,9 @@ use libboard_artiq::si549;
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use libboard_zynq::i2c::I2c;
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use libboard_zynq::timer::GlobalTimer;
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use libconfig::Config;
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use log::{info, warn};
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use log::warn;
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#[cfg(not(feature = "target_ebaz4205"))]
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use log::info;
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#[derive(Debug, PartialEq, Copy, Clone)]
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#[allow(non_camel_case_types)]
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|
|
Loading…
Reference in New Issue