From 62c1765a5f1abf8d5717a8899b7f0f7ec5ce203a Mon Sep 17 00:00:00 2001 From: newell Date: Mon, 30 Sep 2024 09:58:42 -0700 Subject: [PATCH 1/7] Initial gateware --- src/gateware/ebaz4205.py | 252 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 252 insertions(+) create mode 100644 src/gateware/ebaz4205.py diff --git a/src/gateware/ebaz4205.py b/src/gateware/ebaz4205.py new file mode 100644 index 0000000..25b7a2d --- /dev/null +++ b/src/gateware/ebaz4205.py @@ -0,0 +1,252 @@ +#!/usr/bin/env python + +import argparse +from operator import itemgetter + +from migen import * +from migen.build.platforms import ebaz4205 +from migen.build.generic_platform import Pins, Subsignal, IOStandard, Misc +from migen_axi.integration.soc_core import SoCCore +from misoc.interconnect.csr import * + +from artiq.gateware import rtio +from artiq.gateware.rtio.phy import ( + ttl_simple, + dds, # Need to create module for AD9834 +) +from artiq.gateware.rtio.xilinx_clocking import fix_serdes_timing_path + +import dma +import analyzer + +from config import write_csr_file, write_mem_file, write_rustc_cfg_file + +_ps = [ + ( + "ps", + 0, + Subsignal("clk", Pins("E7"), IOStandard("LVCMOS33"), Misc("SLEW=FAST")), + Subsignal("por_b", Pins("C7"), IOStandard("LVCMOS33"), Misc("SLEW=FAST")), + Subsignal("srst_b", Pins("B10"), IOStandard("LVCMOS18"), Misc("SLEW=FAST")), + ) +] + +_ddr = [ + ( + "ddr", + 0, + Subsignal( + "a", + Pins("N2 K2 M3 K3 M4 L1 L4 K4 K1 J4 F5 G4 E4 D4 F4"), + IOStandard("SSTL15"), + ), + Subsignal("ba", Pins("L5 R4 J5"), IOStandard("SSTL15")), + Subsignal("cas_n", Pins("P5"), IOStandard("SSTL15")), + Subsignal("cke", Pins("N3"), IOStandard("SSTL15")), + Subsignal("cs_n", Pins("N1"), IOStandard("SSTL15")), + Subsignal("ck_n", Pins("M2"), IOStandard("DIFF_SSTL15"), Misc("SLEW=FAST")), + Subsignal("ck_p", Pins("L2"), IOStandard("DIFF_SSTL15"), Misc("SLEW=FAST")), + # Pins "T1 Y1" not connected + Subsignal("dm", Pins("A1 F1"), IOStandard("SSTL15_T_DCI"), Misc("SLEW=FAST")), + Subsignal( + "dq", + Pins("C3 B3 A2 A4 D3 D1 C1 E1 E2 E3 G3 H3 J3 H2 H1 J1"), + # Pins "P1 P3 R3 R1 T4 U4 U2 U3 V1 Y3 W1 Y4 Y2 W3 V2 V3" not connected + IOStandard("SSTL15_T_DCI"), + Misc("SLEW=FAST"), + ), + Subsignal( + "dqs_n", + Pins("B2 F2"), # Pins "T2 W4" not connected + IOStandard("DIFF_SSTL15_T_DCI"), + Misc("SLEW=FAST"), + ), + Subsignal( + "dqs_p", + Pins("C2 G2"), # Pins "R2 W5" not connected + IOStandard("DIFF_SSTL15_T_DCI"), + Misc("SLEW=FAST"), + ), + Subsignal("vrn", Pins("G5"), IOStandard("SSTL15_T_DCI"), Misc("SLEW=FAST")), + Subsignal("vrp", Pins("H5"), IOStandard("SSTL15_T_DCI"), Misc("SLEW=FAST")), + Subsignal("drst_n", Pins("B4"), IOStandard("SSTL15"), Misc("SLEW=FAST")), + Subsignal("odt", Pins("N5"), IOStandard("SSTL15")), + Subsignal("ras_n", Pins("P4"), IOStandard("SSTL15")), + Subsignal("we_n", Pins("M5"), IOStandard("SSTL15")), + ) +] + + +class EBAZ4205(SoCCore): + def __init__(self, acpki=False): + self.acpki = acpki + + platform = ebaz4205.Platform() + # platform = Platform() + platform.toolchain.bitstream_commands.extend( + [ + "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]", + ] + ) + platform.add_extension(_ps) + platform.add_extension(_ddr) + + # FCLK is tied to pin U18 + platform.add_extension( + [ + ("fclk", 0, Pins("U18"), IOStandard("LVCMOS33")), + ] + ) + + gmii = platform.request("gmii") + + platform.add_period_constraint(gmii.rx_clk, 10) + platform.add_period_constraint(gmii.tx_clk, 10) + platform.add_platform_command( + "set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets gmii_tx_clk_IBUF]" + ) + + ident = self.__class__.__name__ + if self.acpki: + ident = "acpki_" + ident + SoCCore.__init__( + self, + platform=platform, + csr_data_width=32, + ident=ident, + ) + fix_serdes_timing_path(platform) + # When using pd_cd_sys, the default clock coming from fclk.clk[0] is 100 MHz + self.config["RTIO_FREQUENCY"] = "100" + platform.add_period_constraint(self.ps7.cd_sys.clk, 10) + + self.comb += [ + self.ps7.enet0.enet.gmii.tx_clk.eq(gmii.tx_clk), + self.ps7.enet0.enet.gmii.rx_clk.eq(gmii.rx_clk), + ] + + self.clock_domains.cd_eth_rx = ClockDomain(reset_less=False) + self.clock_domains.cd_eth_tx = ClockDomain(reset_less=False) + self.comb += [ + ClockSignal("eth_rx").eq(gmii.rx_clk), + ClockSignal("eth_tx").eq(gmii.tx_clk), + ] + + self.sync.eth_tx += [ + gmii.txd.eq(self.ps7.enet0.enet.gmii.txd), + gmii.tx_en.eq(self.ps7.enet0.enet.gmii.tx_en), + ] + self.sync.eth_rx += [ + self.ps7.enet0.enet.gmii.rxd.eq(gmii.rxd), + self.ps7.enet0.enet.gmii.rx_dv.eq(gmii.rx_dv), + ] + + # FCLK + fclk = platform.request("fclk") + self.comb += fclk.eq(self.ps7.fclk.clk[0]) + + # MDIO/MDC + mdio = platform.request("mdio") + self.comb += [ + mdio.mdc.eq(self.ps7.enet0.enet.mdio.mdc), + ] + + mdio_t = Signal() + self.comb += mdio_t.eq(~self.ps7.enet0.enet.mdio.t_n) + + self.specials += [ + Instance( + "IOBUF", + i_I=self.ps7.enet0.enet.mdio.o, + io_IO=mdio.mdio, + o_O=self.ps7.enet0.enet.mdio.i, + i_T=mdio_t, + ) + ] + + self.rtio_channels = [] + for i in (0, 1): + print("USER LED at RTIO channel 0x{:06x}".format(len(self.rtio_channels))) + user_led = self.platform.request("user_led", i) + phy = ttl_simple.Output(user_led) + self.submodules += phy + self.rtio_channels.append(rtio.Channel.from_phy(phy)) + self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels) + self.rtio_channels.append(rtio.LogChannel()) + + self.submodules.rtio_tsc = rtio.TSC(glbl_fine_ts_width=3) + self.submodules.rtio_core = rtio.Core(self.rtio_tsc, self.rtio_channels) + self.csr_devices.append("rtio_core") + if self.acpki: + import acpki + + self.config["KI_IMPL"] = "acp" + self.submodules.rtio = acpki.KernelInitiator( + self.rtio_tsc, + bus=self.ps7.s_axi_acp, + user=self.ps7.s_axi_acp_user, + evento=self.ps7.event.o, + ) + self.csr_devices.append("rtio") + else: + self.config["KI_IMPL"] = "csr" + self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True) + self.csr_devices.append("rtio") + + self.submodules.rtio_dma = dma.DMA(self.ps7.s_axi_hp0) + self.csr_devices.append("rtio_dma") + + self.submodules.cri_con = rtio.CRIInterconnectShared( + [self.rtio.cri, self.rtio_dma.cri], + [self.rtio_core.cri], + enable_routing=True, + ) + self.csr_devices.append("cri_con") + + self.submodules.rtio_moninj = rtio.MonInj(self.rtio_channels) + self.csr_devices.append("rtio_moninj") + + self.submodules.rtio_analyzer = analyzer.Analyzer( + self.rtio_tsc, self.rtio_core.cri, self.ps7.s_axi_hp1 + ) + self.csr_devices.append("rtio_analyzer") + + +def main(): + parser = argparse.ArgumentParser( + description="ARTIQ port to the EBAZ4205 control card of Ebit E9+ BTC miner" + ) + parser.add_argument( + "-r", default=None, help="build Rust interface into the specified file" + ) + parser.add_argument( + "-m", default=None, help="build Rust memory interface into the specified file" + ) + parser.add_argument( + "-c", + default=None, + help="build Rust compiler configuration into the specified file", + ) + parser.add_argument( + "-g", default=None, help="build gateware into the specified directory" + ) + parser.add_argument( + "--acpki", default=False, action="store_true", help="enable ACPKI" + ) + args = parser.parse_args() + + soc = EBAZ4205() + soc.finalize() + + if args.r is not None: + write_csr_file(soc, args.r) + if args.m is not None: + write_mem_file(soc, args.m) + if args.c is not None: + write_rustc_cfg_file(soc, args.c) + if args.g is not None: + soc.build(build_dir=args.g) + + +if __name__ == "__main__": + main() -- 2.44.1 From d59c283129221c5025ebc2e3dd5a3b452b91fae1 Mon Sep 17 00:00:00 2001 From: newell Date: Mon, 30 Sep 2024 14:27:54 -0700 Subject: [PATCH 2/7] Update gateware --- src/gateware/ebaz4205.py | 38 +++++++++++++++++--------------------- 1 file changed, 17 insertions(+), 21 deletions(-) diff --git a/src/gateware/ebaz4205.py b/src/gateware/ebaz4205.py index 25b7a2d..744abf3 100644 --- a/src/gateware/ebaz4205.py +++ b/src/gateware/ebaz4205.py @@ -10,10 +10,7 @@ from migen_axi.integration.soc_core import SoCCore from misoc.interconnect.csr import * from artiq.gateware import rtio -from artiq.gateware.rtio.phy import ( - ttl_simple, - dds, # Need to create module for AD9834 -) +from artiq.gateware.rtio.phy import ttl_simple from artiq.gateware.rtio.xilinx_clocking import fix_serdes_timing_path import dma @@ -78,11 +75,10 @@ _ddr = [ class EBAZ4205(SoCCore): - def __init__(self, acpki=False): + def __init__(self, rtio_clk=100e6, acpki=False): self.acpki = acpki platform = ebaz4205.Platform() - # platform = Platform() platform.toolchain.bitstream_commands.extend( [ "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]", @@ -91,12 +87,13 @@ class EBAZ4205(SoCCore): platform.add_extension(_ps) platform.add_extension(_ddr) - # FCLK is tied to pin U18 - platform.add_extension( - [ - ("fclk", 0, Pins("U18"), IOStandard("LVCMOS33")), - ] - ) + ## Uncomment if your EBAZ4205 doesn't have a PHY XTAL + ## Clock for PHY is tied to pin U18 + # platform.add_extension( + # [ + # ("phy_clk", 0, Pins("U18"), IOStandard("LVCMOS33")), + # ] + # ) gmii = platform.request("gmii") @@ -116,22 +113,19 @@ class EBAZ4205(SoCCore): ident=ident, ) fix_serdes_timing_path(platform) - # When using pd_cd_sys, the default clock coming from fclk.clk[0] is 100 MHz - self.config["RTIO_FREQUENCY"] = "100" + self.config["RTIO_FREQUENCY"] = str(rtio_clk / 1e6) platform.add_period_constraint(self.ps7.cd_sys.clk, 10) self.comb += [ self.ps7.enet0.enet.gmii.tx_clk.eq(gmii.tx_clk), self.ps7.enet0.enet.gmii.rx_clk.eq(gmii.rx_clk), ] - self.clock_domains.cd_eth_rx = ClockDomain(reset_less=False) self.clock_domains.cd_eth_tx = ClockDomain(reset_less=False) self.comb += [ ClockSignal("eth_rx").eq(gmii.rx_clk), ClockSignal("eth_tx").eq(gmii.tx_clk), ] - self.sync.eth_tx += [ gmii.txd.eq(self.ps7.enet0.enet.gmii.txd), gmii.tx_en.eq(self.ps7.enet0.enet.gmii.tx_en), @@ -141,11 +135,12 @@ class EBAZ4205(SoCCore): self.ps7.enet0.enet.gmii.rx_dv.eq(gmii.rx_dv), ] - # FCLK - fclk = platform.request("fclk") - self.comb += fclk.eq(self.ps7.fclk.clk[0]) + ## Uncomment if your EBAZ4205 doesn't have a PHY XTAL + ## Left for the user to do, setup a 25 MHz clock for phy_clk. + # phy_clk = platform.request("phy_clk") + # ... - # MDIO/MDC + # MDIO mdio = platform.request("mdio") self.comb += [ mdio.mdc.eq(self.ps7.enet0.enet.mdio.mdc), @@ -230,12 +225,13 @@ def main(): parser.add_argument( "-g", default=None, help="build gateware into the specified directory" ) + parser.add_argument("--rtio_clk", default=100e6, help="RTIO Clock Frequency (Hz)") parser.add_argument( "--acpki", default=False, action="store_true", help="enable ACPKI" ) args = parser.parse_args() - soc = EBAZ4205() + soc = EBAZ4205(rtio_clk=int(args.rtio_clk), acpki=args.acpki) soc.finalize() if args.r is not None: -- 2.44.1 From 0bccf8acca92d0eb49b180163751a1d91c354c65 Mon Sep 17 00:00:00 2001 From: newell Date: Mon, 30 Sep 2024 14:30:30 -0700 Subject: [PATCH 3/7] Include feature for ebaz4205 --- src/libboard_artiq/Cargo.toml.tpl | 1 + src/libksupport/Cargo.toml.tpl | 5 +++++ src/runtime/Cargo.toml.tpl | 1 + 3 files changed, 7 insertions(+) diff --git a/src/libboard_artiq/Cargo.toml.tpl b/src/libboard_artiq/Cargo.toml.tpl index 995fc05..ab8270f 100644 --- a/src/libboard_artiq/Cargo.toml.tpl +++ b/src/libboard_artiq/Cargo.toml.tpl @@ -10,6 +10,7 @@ name = "libboard_artiq" [features] target_zc706 = ["libboard_zynq/target_zc706", "libconfig/target_zc706"] target_kasli_soc = ["libboard_zynq/target_kasli_soc", "libconfig/target_kasli_soc"] +target_ebaz4205 = ["libboard_zynq/target_ebaz4205", "libconfig/target_ebaz4205"] calibrate_wrpll_skew = [] [build-dependencies] diff --git a/src/libksupport/Cargo.toml.tpl b/src/libksupport/Cargo.toml.tpl index 65f9e94..fe873ce 100644 --- a/src/libksupport/Cargo.toml.tpl +++ b/src/libksupport/Cargo.toml.tpl @@ -5,6 +5,11 @@ version = "0.1.0" authors = ["M-Labs"] edition = "2018" +[features] +target_zc706 = [] +target_kasli_soc = [] +target_ebaz4205 = [] + [build-dependencies] build_zynq = { path = "../libbuild_zynq" } diff --git a/src/runtime/Cargo.toml.tpl b/src/runtime/Cargo.toml.tpl index 9f539e0..2818dbb 100644 --- a/src/runtime/Cargo.toml.tpl +++ b/src/runtime/Cargo.toml.tpl @@ -8,6 +8,7 @@ edition = "2018" [features] target_zc706 = ["libboard_zynq/target_zc706", "libsupport_zynq/target_zc706", "libconfig/target_zc706", "libboard_artiq/target_zc706"] target_kasli_soc = ["libboard_zynq/target_kasli_soc", "libsupport_zynq/target_kasli_soc", "libconfig/target_kasli_soc", "libboard_artiq/target_kasli_soc"] +target_ebaz4205 = ["libboard_zynq/target_ebaz4205", "libsupport_zynq/target_ebaz4205", "libconfig/target_ebaz4205", "libboard_artiq/target_ebaz4205", "ksupport/target_ebaz4205"] default = ["target_zc706"] [build-dependencies] -- 2.44.1 From 87f09bed1bf01958d7c087a5f7bb2bb1aa4cd3cb Mon Sep 17 00:00:00 2001 From: newell Date: Mon, 30 Sep 2024 14:31:24 -0700 Subject: [PATCH 4/7] Add configuration flags --- src/libksupport/src/kernel/api.rs | 10 +++++++++- src/libksupport/src/lib.rs | 1 + src/runtime/src/main.rs | 1 + src/runtime/src/rtio_clocking.rs | 4 ++-- 4 files changed, 13 insertions(+), 3 deletions(-) diff --git a/src/libksupport/src/kernel/api.rs b/src/libksupport/src/kernel/api.rs index ef77e43..dc512b5 100644 --- a/src/libksupport/src/kernel/api.rs +++ b/src/libksupport/src/kernel/api.rs @@ -11,7 +11,9 @@ use super::{cache, core1::rtio_get_destination_status, dma, linalg, rpc::{rpc_recv, rpc_send, rpc_send_async}}; -use crate::{eh_artiq, i2c, rtio}; +use crate::{eh_artiq, rtio}; +#[cfg(not(feature = "target_ebaz4205"))] +use crate::i2c; extern "C" { fn vsnprintf_(buffer: *mut c_char, count: size_t, format: *const c_char, va: VaList) -> c_int; @@ -109,11 +111,17 @@ pub fn resolve(required: &[u8]) -> Option { api!(cache_put = cache::put), // i2c + #[cfg(not(feature = "target_ebaz4205"))] api!(i2c_start = i2c::start), + #[cfg(not(feature = "target_ebaz4205"))] api!(i2c_restart = i2c::restart), + #[cfg(not(feature = "target_ebaz4205"))] api!(i2c_stop = i2c::stop), + #[cfg(not(feature = "target_ebaz4205"))] api!(i2c_write = i2c::write), + #[cfg(not(feature = "target_ebaz4205"))] api!(i2c_read = i2c::read), + #[cfg(not(feature = "target_ebaz4205"))] api!(i2c_switch_select = i2c::switch_select), // subkernel diff --git a/src/libksupport/src/lib.rs b/src/libksupport/src/lib.rs index 630f19e..78a2f1d 100644 --- a/src/libksupport/src/lib.rs +++ b/src/libksupport/src/lib.rs @@ -21,6 +21,7 @@ pub use pl::csr::rtio_core; use void::Void; pub mod eh_artiq; +#[cfg(not(feature = "target_ebaz4205"))] pub mod i2c; pub mod irq; pub mod kernel; diff --git a/src/runtime/src/main.rs b/src/runtime/src/main.rs index dd24e25..ecfd1c2 100644 --- a/src/runtime/src/main.rs +++ b/src/runtime/src/main.rs @@ -100,6 +100,7 @@ pub fn main_core0() { info!("gateware ident: {}", identifier_read(&mut [0; 64])); + #[cfg(not(feature = "target_ebaz4205"))] ksupport::i2c::init(); #[cfg(feature = "target_kasli_soc")] { diff --git a/src/runtime/src/rtio_clocking.rs b/src/runtime/src/rtio_clocking.rs index 06918b2..42cb215 100644 --- a/src/runtime/src/rtio_clocking.rs +++ b/src/runtime/src/rtio_clocking.rs @@ -69,7 +69,7 @@ fn get_rtio_clock_cfg(cfg: &Config) -> RtioClock { res } -#[cfg(not(has_drtio))] +#[cfg(not(any(has_drtio, feature = "target_ebaz4205")))] fn init_rtio(timer: &mut GlobalTimer) { info!("Switching SYS clocks..."); unsafe { @@ -429,7 +429,7 @@ pub fn init(timer: &mut GlobalTimer, cfg: &Config) { #[cfg(has_drtio)] init_drtio(timer); - #[cfg(not(has_drtio))] + #[cfg(not(any(has_drtio, feature = "target_ebaz4205")))] init_rtio(timer); #[cfg(all(has_si549, has_wrpll))] -- 2.44.1 From b2a741437d805069f2df6b3a5a2c53045bf2658b Mon Sep 17 00:00:00 2001 From: newell Date: Mon, 30 Sep 2024 20:56:56 -0700 Subject: [PATCH 5/7] Remove commented code for PHY xtal. --- src/gateware/ebaz4205.py | 14 -------------- 1 file changed, 14 deletions(-) diff --git a/src/gateware/ebaz4205.py b/src/gateware/ebaz4205.py index 744abf3..3359a10 100644 --- a/src/gateware/ebaz4205.py +++ b/src/gateware/ebaz4205.py @@ -87,16 +87,7 @@ class EBAZ4205(SoCCore): platform.add_extension(_ps) platform.add_extension(_ddr) - ## Uncomment if your EBAZ4205 doesn't have a PHY XTAL - ## Clock for PHY is tied to pin U18 - # platform.add_extension( - # [ - # ("phy_clk", 0, Pins("U18"), IOStandard("LVCMOS33")), - # ] - # ) - gmii = platform.request("gmii") - platform.add_period_constraint(gmii.rx_clk, 10) platform.add_period_constraint(gmii.tx_clk, 10) platform.add_platform_command( @@ -135,11 +126,6 @@ class EBAZ4205(SoCCore): self.ps7.enet0.enet.gmii.rx_dv.eq(gmii.rx_dv), ] - ## Uncomment if your EBAZ4205 doesn't have a PHY XTAL - ## Left for the user to do, setup a 25 MHz clock for phy_clk. - # phy_clk = platform.request("phy_clk") - # ... - # MDIO mdio = platform.request("mdio") self.comb += [ -- 2.44.1 From da8817064a64ee72f33f71aee1e69d34f960646e Mon Sep 17 00:00:00 2001 From: newell Date: Fri, 4 Oct 2024 23:45:24 -0700 Subject: [PATCH 6/7] Add i2c support --- src/gateware/ebaz4205.py | 57 ++++++++++++++++++++----------- src/libksupport/src/kernel/api.rs | 10 +----- src/libksupport/src/lib.rs | 1 - src/runtime/src/main.rs | 1 - src/runtime/src/rtio_clocking.rs | 6 +++- 5 files changed, 44 insertions(+), 31 deletions(-) diff --git a/src/gateware/ebaz4205.py b/src/gateware/ebaz4205.py index 3359a10..be360da 100644 --- a/src/gateware/ebaz4205.py +++ b/src/gateware/ebaz4205.py @@ -73,9 +73,19 @@ _ddr = [ ) ] +# Connector J3 +_i2c = [ + ( + "i2c", + 0, + Subsignal("scl", Pins("U12"), IOStandard("LVCMOS33")), + Subsignal("sda", Pins("V13"), IOStandard("LVCMOS33")), + ) +] + class EBAZ4205(SoCCore): - def __init__(self, rtio_clk=100e6, acpki=False): + def __init__(self, rtio_clk=125e6, acpki=False): self.acpki = acpki platform = ebaz4205.Platform() @@ -86,6 +96,7 @@ class EBAZ4205(SoCCore): ) platform.add_extension(_ps) platform.add_extension(_ddr) + platform.add_extension(_i2c) gmii = platform.request("gmii") platform.add_period_constraint(gmii.rx_clk, 10) @@ -97,12 +108,7 @@ class EBAZ4205(SoCCore): ident = self.__class__.__name__ if self.acpki: ident = "acpki_" + ident - SoCCore.__init__( - self, - platform=platform, - csr_data_width=32, - ident=ident, - ) + SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident) fix_serdes_timing_path(platform) self.config["RTIO_FREQUENCY"] = str(rtio_clk / 1e6) platform.add_period_constraint(self.ps7.cd_sys.clk, 10) @@ -128,21 +134,34 @@ class EBAZ4205(SoCCore): # MDIO mdio = platform.request("mdio") - self.comb += [ - mdio.mdc.eq(self.ps7.enet0.enet.mdio.mdc), - ] - - mdio_t = Signal() - self.comb += mdio_t.eq(~self.ps7.enet0.enet.mdio.t_n) + self.comb += mdio.mdc.eq(self.ps7.enet0.enet.mdio.mdc) + self.specials += Instance( + "IOBUF", + i_I=self.ps7.enet0.enet.mdio.o, + io_IO=mdio.mdio, + o_O=self.ps7.enet0.enet.mdio.i, + i_T=~self.ps7.enet0.enet.mdio.t_n, + ) + # I2C + i2c = self.platform.request("i2c") self.specials += [ + # SCL Instance( "IOBUF", - i_I=self.ps7.enet0.enet.mdio.o, - io_IO=mdio.mdio, - o_O=self.ps7.enet0.enet.mdio.i, - i_T=mdio_t, - ) + i_I=self.ps7.i2c0.scl.o, + io_IO=i2c.scl, + o_O=self.ps7.i2c0.scl.i, + i_T=~self.ps7.i2c0.scl.t_n, + ), + # SDA + Instance( + "IOBUF", + i_I=self.ps7.i2c0.sda.o, + io_IO=i2c.sda, + o_O=self.ps7.i2c0.sda.i, + i_T=~self.ps7.i2c0.sda.t_n, + ), ] self.rtio_channels = [] @@ -211,7 +230,7 @@ def main(): parser.add_argument( "-g", default=None, help="build gateware into the specified directory" ) - parser.add_argument("--rtio_clk", default=100e6, help="RTIO Clock Frequency (Hz)") + parser.add_argument("--rtio-clk", default=125e6, help="RTIO Clock Frequency (Hz)") parser.add_argument( "--acpki", default=False, action="store_true", help="enable ACPKI" ) diff --git a/src/libksupport/src/kernel/api.rs b/src/libksupport/src/kernel/api.rs index dc512b5..ef77e43 100644 --- a/src/libksupport/src/kernel/api.rs +++ b/src/libksupport/src/kernel/api.rs @@ -11,9 +11,7 @@ use super::{cache, core1::rtio_get_destination_status, dma, linalg, rpc::{rpc_recv, rpc_send, rpc_send_async}}; -use crate::{eh_artiq, rtio}; -#[cfg(not(feature = "target_ebaz4205"))] -use crate::i2c; +use crate::{eh_artiq, i2c, rtio}; extern "C" { fn vsnprintf_(buffer: *mut c_char, count: size_t, format: *const c_char, va: VaList) -> c_int; @@ -111,17 +109,11 @@ pub fn resolve(required: &[u8]) -> Option { api!(cache_put = cache::put), // i2c - #[cfg(not(feature = "target_ebaz4205"))] api!(i2c_start = i2c::start), - #[cfg(not(feature = "target_ebaz4205"))] api!(i2c_restart = i2c::restart), - #[cfg(not(feature = "target_ebaz4205"))] api!(i2c_stop = i2c::stop), - #[cfg(not(feature = "target_ebaz4205"))] api!(i2c_write = i2c::write), - #[cfg(not(feature = "target_ebaz4205"))] api!(i2c_read = i2c::read), - #[cfg(not(feature = "target_ebaz4205"))] api!(i2c_switch_select = i2c::switch_select), // subkernel diff --git a/src/libksupport/src/lib.rs b/src/libksupport/src/lib.rs index 78a2f1d..630f19e 100644 --- a/src/libksupport/src/lib.rs +++ b/src/libksupport/src/lib.rs @@ -21,7 +21,6 @@ pub use pl::csr::rtio_core; use void::Void; pub mod eh_artiq; -#[cfg(not(feature = "target_ebaz4205"))] pub mod i2c; pub mod irq; pub mod kernel; diff --git a/src/runtime/src/main.rs b/src/runtime/src/main.rs index ecfd1c2..dd24e25 100644 --- a/src/runtime/src/main.rs +++ b/src/runtime/src/main.rs @@ -100,7 +100,6 @@ pub fn main_core0() { info!("gateware ident: {}", identifier_read(&mut [0; 64])); - #[cfg(not(feature = "target_ebaz4205"))] ksupport::i2c::init(); #[cfg(feature = "target_kasli_soc")] { diff --git a/src/runtime/src/rtio_clocking.rs b/src/runtime/src/rtio_clocking.rs index 42cb215..cf464c1 100644 --- a/src/runtime/src/rtio_clocking.rs +++ b/src/runtime/src/rtio_clocking.rs @@ -1,6 +1,8 @@ +#[cfg(not(feature = "target_ebaz4205"))] use embedded_hal::blocking::delay::DelayMs; #[cfg(has_si5324)] use ksupport::i2c; +#[cfg(not(feature = "target_ebaz4205"))] use libboard_artiq::pl; #[cfg(has_si5324)] use libboard_artiq::si5324; @@ -10,7 +12,9 @@ use libboard_artiq::si549; use libboard_zynq::i2c::I2c; use libboard_zynq::timer::GlobalTimer; use libconfig::Config; -use log::{info, warn}; +use log::warn; +#[cfg(not(feature = "target_ebaz4205"))] +use log::info; #[derive(Debug, PartialEq, Copy, Clone)] #[allow(non_camel_case_types)] -- 2.44.1 From db62ef89f0584b93f8b9e5a35b1ddded798a3b0e Mon Sep 17 00:00:00 2001 From: newell Date: Fri, 4 Oct 2024 23:58:54 -0700 Subject: [PATCH 7/7] Update Cargo templates --- src/libksupport/Cargo.toml.tpl | 5 ----- src/runtime/Cargo.toml.tpl | 2 +- 2 files changed, 1 insertion(+), 6 deletions(-) diff --git a/src/libksupport/Cargo.toml.tpl b/src/libksupport/Cargo.toml.tpl index fe873ce..65f9e94 100644 --- a/src/libksupport/Cargo.toml.tpl +++ b/src/libksupport/Cargo.toml.tpl @@ -5,11 +5,6 @@ version = "0.1.0" authors = ["M-Labs"] edition = "2018" -[features] -target_zc706 = [] -target_kasli_soc = [] -target_ebaz4205 = [] - [build-dependencies] build_zynq = { path = "../libbuild_zynq" } diff --git a/src/runtime/Cargo.toml.tpl b/src/runtime/Cargo.toml.tpl index 2818dbb..c844131 100644 --- a/src/runtime/Cargo.toml.tpl +++ b/src/runtime/Cargo.toml.tpl @@ -8,7 +8,7 @@ edition = "2018" [features] target_zc706 = ["libboard_zynq/target_zc706", "libsupport_zynq/target_zc706", "libconfig/target_zc706", "libboard_artiq/target_zc706"] target_kasli_soc = ["libboard_zynq/target_kasli_soc", "libsupport_zynq/target_kasli_soc", "libconfig/target_kasli_soc", "libboard_artiq/target_kasli_soc"] -target_ebaz4205 = ["libboard_zynq/target_ebaz4205", "libsupport_zynq/target_ebaz4205", "libconfig/target_ebaz4205", "libboard_artiq/target_ebaz4205", "ksupport/target_ebaz4205"] +target_ebaz4205 = ["libboard_zynq/target_ebaz4205", "libsupport_zynq/target_ebaz4205", "libconfig/target_ebaz4205", "libboard_artiq/target_ebaz4205"] default = ["target_zc706"] [build-dependencies] -- 2.44.1