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Add ebaz4205 support #327

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sb10q merged 7 commits from newell/artiq-zynq:ebaz4205 into master 2024-10-05 15:05:54 +08:00
Conversation 0 Commits 7 Files Changed 4 +17 -21
1 changed files with 17 additions and 21 deletions
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src/gateware/ebaz4205.py
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@ -10,10 +10,7 @@ from migen_axi.integration.soc_core import SoCCore
from misoc.interconnect.csr import * from misoc.interconnect.csr import *
from artiq.gateware import rtio from artiq.gateware import rtio
from artiq.gateware.rtio.phy import ( from artiq.gateware.rtio.phy import ttl_simple
ttl_simple,
dds, # Need to create module for AD9834
)
from artiq.gateware.rtio.xilinx_clocking import fix_serdes_timing_path from artiq.gateware.rtio.xilinx_clocking import fix_serdes_timing_path
import dma import dma
@ -78,11 +75,10 @@ _ddr = [
class EBAZ4205(SoCCore): class EBAZ4205(SoCCore):
def __init__(self, acpki=False): def __init__(self, rtio_clk=100e6, acpki=False):
self.acpki = acpki self.acpki = acpki
platform = ebaz4205.Platform() platform = ebaz4205.Platform()
# platform = Platform()
platform.toolchain.bitstream_commands.extend( platform.toolchain.bitstream_commands.extend(
[ [
"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]", "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
@ -91,12 +87,13 @@ class EBAZ4205(SoCCore):
platform.add_extension(_ps) platform.add_extension(_ps)
platform.add_extension(_ddr) platform.add_extension(_ddr)
# FCLK is tied to pin U18 ## Uncomment if your EBAZ4205 doesn't have a PHY XTAL
newell marked this conversation as resolved Outdated
mwojcik commented 2024-10-01 10:26:28 +08:00
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This should be a commandline option (e.g. --no-xtal), rather than uncommenting

This should be a commandline option (e.g. ``--no-xtal``), rather than uncommenting
newell commented 2024-10-01 11:45:10 +08:00
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Yes, agreed. This board is known to come in different variants on the 2nd hand market and I don't feel like removing the xtal to test things as my board has the xtal populated. I will remove this commented out code and leave the commandline option for a possible future branch.

Yes, agreed. This board is known to come in different variants on the 2nd hand market and I don't feel like removing the xtal to test things as my board has the xtal populated. I will remove this commented out code and leave the commandline option for a possible future branch.
mwojcik commented 2024-10-01 12:47:08 +08:00
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Fair enough, don't add anything that's not been tested either.

Fair enough, don't add anything that's not been tested either.
platform.add_extension( ## Clock for PHY is tied to pin U18
[ # platform.add_extension(
("fclk", 0, Pins("U18"), IOStandard("LVCMOS33")), # [
] # ("phy_clk", 0, Pins("U18"), IOStandard("LVCMOS33")),
) # ]
# )
gmii = platform.request("gmii") gmii = platform.request("gmii")
@ -116,22 +113,19 @@ class EBAZ4205(SoCCore):
ident=ident, ident=ident,
) )
fix_serdes_timing_path(platform) fix_serdes_timing_path(platform)
# When using pd_cd_sys, the default clock coming from fclk.clk[0] is 100 MHz self.config["RTIO_FREQUENCY"] = str(rtio_clk / 1e6)
self.config["RTIO_FREQUENCY"] = "100"
platform.add_period_constraint(self.ps7.cd_sys.clk, 10) platform.add_period_constraint(self.ps7.cd_sys.clk, 10)
self.comb += [ self.comb += [
self.ps7.enet0.enet.gmii.tx_clk.eq(gmii.tx_clk), self.ps7.enet0.enet.gmii.tx_clk.eq(gmii.tx_clk),
self.ps7.enet0.enet.gmii.rx_clk.eq(gmii.rx_clk), self.ps7.enet0.enet.gmii.rx_clk.eq(gmii.rx_clk),
] ]
self.clock_domains.cd_eth_rx = ClockDomain(reset_less=False) self.clock_domains.cd_eth_rx = ClockDomain(reset_less=False)
self.clock_domains.cd_eth_tx = ClockDomain(reset_less=False) self.clock_domains.cd_eth_tx = ClockDomain(reset_less=False)
self.comb += [ self.comb += [
ClockSignal("eth_rx").eq(gmii.rx_clk), ClockSignal("eth_rx").eq(gmii.rx_clk),
ClockSignal("eth_tx").eq(gmii.tx_clk), ClockSignal("eth_tx").eq(gmii.tx_clk),
] ]
self.sync.eth_tx += [ self.sync.eth_tx += [
gmii.txd.eq(self.ps7.enet0.enet.gmii.txd), gmii.txd.eq(self.ps7.enet0.enet.gmii.txd),
gmii.tx_en.eq(self.ps7.enet0.enet.gmii.tx_en), gmii.tx_en.eq(self.ps7.enet0.enet.gmii.tx_en),
@ -141,11 +135,12 @@ class EBAZ4205(SoCCore):
self.ps7.enet0.enet.gmii.rx_dv.eq(gmii.rx_dv), self.ps7.enet0.enet.gmii.rx_dv.eq(gmii.rx_dv),
] ]
# FCLK ## Uncomment if your EBAZ4205 doesn't have a PHY XTAL
fclk = platform.request("fclk") ## Left for the user to do, setup a 25 MHz clock for phy_clk.
self.comb += fclk.eq(self.ps7.fclk.clk[0]) # phy_clk = platform.request("phy_clk")
# ...
# MDIO/MDC # MDIO
mdio = platform.request("mdio") mdio = platform.request("mdio")
self.comb += [ self.comb += [
mdio.mdc.eq(self.ps7.enet0.enet.mdio.mdc), mdio.mdc.eq(self.ps7.enet0.enet.mdio.mdc),
@ -230,12 +225,13 @@ def main():
parser.add_argument( parser.add_argument(
"-g", default=None, help="build gateware into the specified directory" "-g", default=None, help="build gateware into the specified directory"
) )
parser.add_argument("--rtio_clk", default=100e6, help="RTIO Clock Frequency (Hz)")
parser.add_argument( parser.add_argument(
"--acpki", default=False, action="store_true", help="enable ACPKI" "--acpki", default=False, action="store_true", help="enable ACPKI"
) )
args = parser.parse_args() args = parser.parse_args()
soc = EBAZ4205() soc = EBAZ4205(rtio_clk=int(args.rtio_clk), acpki=args.acpki)
soc.finalize() soc.finalize()
if args.r is not None: if args.r is not None: