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Add ebaz4205 support #327

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sb10q merged 7 commits from newell/artiq-zynq:ebaz4205 into master 2024-10-05 15:05:54 +08:00
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src/gateware/ebaz4205.py
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@ -87,16 +87,7 @@ class EBAZ4205(SoCCore):
platform.add_extension(_ps) platform.add_extension(_ps)
platform.add_extension(_ddr) platform.add_extension(_ddr)
## Uncomment if your EBAZ4205 doesn't have a PHY XTAL
## Clock for PHY is tied to pin U18
# platform.add_extension(
# [
# ("phy_clk", 0, Pins("U18"), IOStandard("LVCMOS33")),
# ]
# )
gmii = platform.request("gmii") gmii = platform.request("gmii")
platform.add_period_constraint(gmii.rx_clk, 10) platform.add_period_constraint(gmii.rx_clk, 10)
platform.add_period_constraint(gmii.tx_clk, 10) platform.add_period_constraint(gmii.tx_clk, 10)
platform.add_platform_command( platform.add_platform_command(
@ -135,11 +126,6 @@ class EBAZ4205(SoCCore):
self.ps7.enet0.enet.gmii.rx_dv.eq(gmii.rx_dv), self.ps7.enet0.enet.gmii.rx_dv.eq(gmii.rx_dv),
] ]
## Uncomment if your EBAZ4205 doesn't have a PHY XTAL
## Left for the user to do, setup a 25 MHz clock for phy_clk.
# phy_clk = platform.request("phy_clk")
# ...
# MDIO # MDIO
mdio = platform.request("mdio") mdio = platform.request("mdio")
self.comb += [ self.comb += [