M-Labs
/
artiq-zynq
10
1
Fork 19
Code Issues 12 Pull Requests Releases Wiki Activity

DDMTD: replace FD with ISERDESE2 #292

Merged
sb10q merged 2 commits from morgan/artiq-zynq:DDMTD into master 2024-04-29 13:03:30 +08:00
Conversation 0 Commits 2 Files Changed 2 +39 -13
2 changed files with 39 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

48
src/gateware/ddmtd.py
View File

@ -10,18 +10,44 @@ class DDMTDSampler(Module):
# # #
sb10q commented 2024-04-29 11:20:05 +08:00
Outdated
Review
Copy Link

Move closer to IDELAYE2 instantiation. This is just an internal signal used to make routing possible, not part of the module's interface.

Move closer to IDELAYE2 instantiation. This is just an internal signal used to make routing possible, not part of the module's interface.
ref_beating_FF = Signal()
main_beating_FF = Signal()
ref_clk = Signal()
self.specials +=[
# Two back to back FFs are used to prevent metastability
Instance("FD", i_C=ClockSignal("helper"),
i_D=cd_ref.clk, o_Q=ref_beating_FF),
Instance("FD", i_C=ClockSignal("helper"),
i_D=ref_beating_FF, o_Q=self.ref_beating),
Instance("FD", i_C=ClockSignal("helper"),
i_D=main_clk_se, o_Q=main_beating_FF),
Instance("FD", i_C=ClockSignal("helper"),
i_D=main_beating_FF, o_Q=self.main_beating)
# ISERDESE2 can only be driven from fabric via IDELAYE2 (see UG471)
Instance("IDELAYE2",
p_DELAY_SRC="DATAIN",
p_HIGH_PERFORMANCE_MODE="TRUE",
p_REFCLK_FREQUENCY=208.3, # REFCLK frequency from IDELAYCTRL
p_IDELAY_VALUE=0,
i_DATAIN=cd_ref.clk,
o_DATAOUT=ref_clk
),
Instance("ISERDESE2",
p_IOBDELAY="IFD", # use DDLY as input
p_DATA_RATE="SDR",
p_DATA_WIDTH=2, # min is 2
p_NUM_CE=1,
i_DDLY=ref_clk,
i_CE1=1,
i_CLK=ClockSignal("helper"),
i_CLKDIV=ClockSignal("helper"),
o_Q1=self.ref_beating
),
Instance("ISERDESE2",
p_DATA_RATE="SDR",
p_DATA_WIDTH=2, # min is 2
p_NUM_CE=1,
i_D=main_clk_se,
i_CE1=1,
i_CLK=ClockSignal("helper"),
i_CLKDIV=ClockSignal("helper"),
o_Q1=self.main_beating,
),
]

2
src/libboard_artiq/src/si549.rs
View File

@ -356,7 +356,7 @@ pub mod wrpll {
use super::*;
#[cfg(wrpll_ref_clk = "GT_CDR")]
static mut TAG_OFFSET: u32 = 19050;
static mut TAG_OFFSET: u32 = 8382;
#[cfg(wrpll_ref_clk = "SMA_CLKIN")]
static mut TAG_OFFSET: u32 = 0;
static mut REF_TAG: u32 = 0;