DDMTD: replace FD with ISERDESE2 #292

Merged
sb10q merged 2 commits from morgan/artiq-zynq:DDMTD into master 2024-04-29 13:03:30 +08:00

Summary

  • around 0.5-1dB "knee" improvement for SMACLKin, but for CDR the effect is less noticeable
  • DDMTD: replace FD with ISERDESE2
    • IDELAYE2 is added for ref_clk, since ISERDESE2 can only be driven via IOB (i_D) or IDELAY (i_DDLY)
    • using one Flip Flop only, as the setup/hold of ISERDESE2 is much better
  • Si549: update TAG_OFFSET to meet the setup/hold constraints of rx synchronizer
    • 8382 (41150 mod 0x8000) is used as the calibrated tag offset, it's the average result of 10 consecutive runs on one of the card.
INFO(libboard_artiq::si549::wrpll): calibration successful, error zone: 24160 -> 25208, width: 31720 (348deg), middle of working region: 41068
INFO(libboard_artiq::si549::wrpll): calibration successful, error zone: 24552 -> 25424, width: 31896 (350deg), middle of working region: 41372
INFO(libboard_artiq::si549::wrpll): calibration successful, error zone: 24168 -> 25016, width: 31920 (350deg), middle of working region: 40976
INFO(libboard_artiq::si549::wrpll): calibration successful, error zone: 24320 -> 25144, width: 31944 (350deg), middle of working region: 41116
INFO(libboard_artiq::si549::wrpll): calibration successful, error zone: 24344 -> 25160, width: 31952 (351deg), middle of working region: 41136
INFO(libboard_artiq::si549::wrpll): calibration successful, error zone: 24336 -> 25128, width: 31976 (351deg), middle of working region: 41116
INFO(libboard_artiq::si549::wrpll): calibration successful, error zone: 24584 -> 25376, width: 31976 (351deg), middle of working region: 41364
INFO(libboard_artiq::si549::wrpll): calibration successful, error zone: 24336 -> 25104, width: 32000 (351deg), middle of working region: 41104
INFO(libboard_artiq::si549::wrpll): calibration successful, error zone: 24336 -> 25088, width: 32016 (351deg), middle of working region: 41096
INFO(libboard_artiq::si549::wrpll): calibration successful, error zone: 24360 -> 25120, width: 32008 (351deg), middle of working region: 41124

Phase noise measurement

  • Synth 125MHz <-> Standalone is mesaured
    ISERDES
## Summary - around 0.5-1dB "knee" improvement for SMACLKin, but for CDR the effect is less noticeable - DDMTD: replace `FD` with `ISERDESE2` - `IDELAYE2` is added for ref_clk, since `ISERDESE2` can only be driven via IOB (i_D) or IDELAY (i_DDLY) - using one Flip Flop only, as the setup/hold of ISERDESE2 is much better - Si549: update `TAG_OFFSET` to meet the setup/hold constraints of rx synchronizer - 8382 (41150 mod 0x8000) is used as the calibrated tag offset, it's the average result of 10 consecutive runs on one of the card. ```bash INFO(libboard_artiq::si549::wrpll): calibration successful, error zone: 24160 -> 25208, width: 31720 (348deg), middle of working region: 41068 INFO(libboard_artiq::si549::wrpll): calibration successful, error zone: 24552 -> 25424, width: 31896 (350deg), middle of working region: 41372 INFO(libboard_artiq::si549::wrpll): calibration successful, error zone: 24168 -> 25016, width: 31920 (350deg), middle of working region: 40976 INFO(libboard_artiq::si549::wrpll): calibration successful, error zone: 24320 -> 25144, width: 31944 (350deg), middle of working region: 41116 INFO(libboard_artiq::si549::wrpll): calibration successful, error zone: 24344 -> 25160, width: 31952 (351deg), middle of working region: 41136 INFO(libboard_artiq::si549::wrpll): calibration successful, error zone: 24336 -> 25128, width: 31976 (351deg), middle of working region: 41116 INFO(libboard_artiq::si549::wrpll): calibration successful, error zone: 24584 -> 25376, width: 31976 (351deg), middle of working region: 41364 INFO(libboard_artiq::si549::wrpll): calibration successful, error zone: 24336 -> 25104, width: 32000 (351deg), middle of working region: 41104 INFO(libboard_artiq::si549::wrpll): calibration successful, error zone: 24336 -> 25088, width: 32016 (351deg), middle of working region: 41096 INFO(libboard_artiq::si549::wrpll): calibration successful, error zone: 24360 -> 25120, width: 32008 (351deg), middle of working region: 41124 ``` ## Phase noise measurement - Synth 125MHz <-> Standalone is mesaured ![ISERDES](/attachments/bcc44573-12eb-41ea-8e78-36e8beab555c)
morgan added 2 commits 2024-04-26 12:44:32 +08:00
sb10q reviewed 2024-04-29 11:20:05 +08:00
@ -8,20 +8,47 @@ class DDMTDSampler(Module):
self.ref_beating = Signal()
self.main_beating = Signal()
ref_clk = Signal()

Move closer to IDELAYE2 instantiation. This is just an internal signal used to make routing possible, not part of the module's interface.

Move closer to IDELAYE2 instantiation. This is just an internal signal used to make routing possible, not part of the module's interface.
morgan force-pushed DDMTD from 86ccbf16d0 to 11072f3aff 2024-04-29 12:06:00 +08:00 Compare
sb10q merged commit 61315c29b9 into master 2024-04-29 13:03:30 +08:00
Sign in to join this conversation.
No reviewers
No Milestone
No Assignees
2 Participants
Notifications
Due Date
The due date is invalid or out of range. Please use the format 'yyyy-mm-dd'.

No due date set.

Dependencies

No dependencies set.

Reference: M-Labs/artiq-zynq#292
There is no content yet.