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DDMTD: replace FD with ISERDESE2 #292

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sb10q merged 2 commits from morgan/artiq-zynq:DDMTD into master 2024-04-29 13:03:30 +08:00
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1 changed files with 38 additions and 12 deletions
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src/gateware/ddmtd.py
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@ -10,18 +10,44 @@ class DDMTDSampler(Module):
# # # # # #
ref_beating_FF = Signal() ref_clk = Signal()
main_beating_FF = Signal()
self.specials +=[ self.specials +=[
# Two back to back FFs are used to prevent metastability # ISERDESE2 can only be driven from fabric via IDELAYE2 (see UG471)
Instance("FD", i_C=ClockSignal("helper"), Instance("IDELAYE2",
i_D=cd_ref.clk, o_Q=ref_beating_FF), p_DELAY_SRC="DATAIN",
Instance("FD", i_C=ClockSignal("helper"), p_HIGH_PERFORMANCE_MODE="TRUE",
i_D=ref_beating_FF, o_Q=self.ref_beating), p_REFCLK_FREQUENCY=208.3, # REFCLK frequency from IDELAYCTRL
Instance("FD", i_C=ClockSignal("helper"), p_IDELAY_VALUE=0,
i_D=main_clk_se, o_Q=main_beating_FF),
Instance("FD", i_C=ClockSignal("helper"), i_DATAIN=cd_ref.clk,
i_D=main_beating_FF, o_Q=self.main_beating)
o_DATAOUT=ref_clk
),
Instance("ISERDESE2",
p_IOBDELAY="IFD", # use DDLY as input
p_DATA_RATE="SDR",
p_DATA_WIDTH=2, # min is 2
p_NUM_CE=1,
i_DDLY=ref_clk,
i_CE1=1,
i_CLK=ClockSignal("helper"),
i_CLKDIV=ClockSignal("helper"),
o_Q1=self.ref_beating
),
Instance("ISERDESE2",
p_DATA_RATE="SDR",
p_DATA_WIDTH=2, # min is 2
p_NUM_CE=1,
i_D=main_clk_se,
i_CE1=1,
i_CLK=ClockSignal("helper"),
i_CLKDIV=ClockSignal("helper"),
o_Q1=self.main_beating,
),
] ]