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Subkernels: support sub-subkernels, DRTIO routing #281

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sb10q merged 3 commits from mwojcik/artiq-zynq:drtio_routing into master 2024-01-11 12:33:10 +08:00
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mwojcik commented 2023-12-12 17:13:44 +08:00
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Port of artiq#2291, which is required as base.

Tested successfully in both configurations:

  • Chain: Satellite as far position (rank 2) with 2.0 satellite above,
  • Chain: Satellite in middle position (rank 1) with 2.0 sub-sat,
  • Chain: Master (with two 2.0 satellites),
  • Star: Satellite (with 2.0 master, + another 2.0 satellite),
  • Star: Master (with 2 2.0 satellites).

Also:

  • (D)DMA as satellite
  • (D)DMA as master
Port of [artiq#2291](https://github.com/m-labs/artiq/pull/2291), which is required as base. Tested successfully in both configurations: * [x] Chain: Satellite as far position (rank 2) with 2.0 satellite above, * [x] Chain: Satellite in middle position (rank 1) with 2.0 sub-sat, * [x] Chain: Master (with two 2.0 satellites), * [x] Star: Satellite (with 2.0 master, + another 2.0 satellite), * [x] Star: Master (with 2 2.0 satellites). Also: * [x] (D)DMA as satellite * [x] (D)DMA as master
mwojcik force-pushed drtio_routing from 7d30100a88 to 60a34468eb 2023-12-12 17:43:13 +08:00 Compare
mwojcik force-pushed drtio_routing from 60a34468eb to 872895e769 2023-12-13 17:35:04 +08:00 Compare
mwojcik force-pushed drtio_routing from 872895e769 to 96cb71ccdc 2023-12-14 15:17:05 +08:00 Compare
mwojcik force-pushed drtio_routing from 96cb71ccdc to 4271a94354 2023-12-14 15:19:22 +08:00 Compare
mwojcik force-pushed drtio_routing from 4271a94354 to 0dd834acf8 2023-12-14 16:37:16 +08:00 Compare
mwojcik force-pushed drtio_routing from dece5b5d3b to f4aa015be6 2024-01-10 14:11:31 +08:00 Compare
mwojcik force-pushed drtio_routing from f4aa015be6 to 2c33208fb1 2024-01-10 15:42:32 +08:00 Compare
mwojcik commented 2024-01-10 17:20:37 +08:00
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(D)DMA also supported - a bit different from RISC-V since the kernel core does not have separate CSR devices.

What's left after this is free message passing - I believe only on the compiler side.

(D)DMA also supported - a bit different from RISC-V since the kernel core does not have separate CSR devices. What's left after this is free message passing - I believe only on the compiler side.
sb10q merged commit 30e6bf4a3a into master 2024-01-11 12:33:07 +08:00
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Reference: M-Labs/artiq-zynq#281
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