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szl: enabled FPU #27

Merged
sb10q merged 1 commits from pca006132/artiq-zynq:master into master 2020-07-02 20:02:51 +08:00
Conversation 1 Commits 1 Files Changed 2
2 changed files with 14 additions and 1 deletions
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2
src/szl/build.rs
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@ -31,7 +31,7 @@ pub fn compile_unlzma() {
cfg.flag("-ffreestanding");
cfg.flag("-fPIC");
cfg.flag("-fno-stack-protector");
cfg.flag("--target=armv7-unknown-linux");
cfg.flag("--target=armv7-none-eabihf");
cfg.flag("-O2");
let sources = vec![

13
src/szl/src/main.rs
View File

@ -1,5 +1,6 @@
#![no_std]
#![no_main]
#![feature(llvm_asm)]
extern crate log;
@ -36,6 +37,18 @@ pub fn main_core0() {
log::set_max_level(log::LevelFilter::Debug);
info!("Simple Zynq Loader starting...");
unsafe {
sb10q commented 2020-07-02 20:02:20 +08:00
Review

Maybe this should be moved into zc706 (cortexa9 library), since it's generic and also now used in several places.

Maybe this should be moved into zc706 (cortexa9 library), since it's generic and also now used in several places.
llvm_asm!("
mrc p15, 0, r1, c1, c0, 2
orr r1, r1, (0b1111<<20)
mcr p15, 0, r1, c1, c0, 2
vmrs r1, fpexc
orr r1, r1, (1<<30)
vmsr fpexc, r1
":::"r1");
}
info!("FPU enabled on Core0");
const CPU_FREQ: u32 = 800_000_000;
ArmPll::setup(2 * CPU_FREQ);