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kasli-soc: Add BUFG to the IBUFGDS for MMCM CLKIN1 #269

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sb10q merged 1 commits from linuswck/artiq-zynq:kasli_soc_demo_add_bufg_to_clk_synth into master 2023-10-11 16:45:26 +08:00
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linuswck commented 2023-10-11 15:25:42 +08:00
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This PR fixes DRC REQP-119 on kasli-soc-demo gateware compilation.

Adding BUFG to IBUFGDS make CLKIN1 and CLKIN2 in MMCME2_ADV have the same source type, which is required for MMCME2_ADV suggested by the error message.

Original Error Message

[DRC REQP-119] V7V8V9_MMCM_SET_COMPENSATION0: Cell MMCME2_ADV of type 'MMCME2_ADV' has CLKIN1 and CLKIN2 driven from different source types. The different timing on these paths require different COMPENSATION settings which is not supported by the hardware. When using an MMCM in clock switchover mode, the two source inputs must be driven from the same type of resource.
This PR fixes DRC REQP-119 on `kasli-soc-demo` gateware compilation. Adding BUFG to IBUFGDS make CLKIN1 and CLKIN2 in MMCME2_ADV have the same source type, which is required for MMCME2_ADV suggested by the error message. Original Error Message ```TCL [DRC REQP-119] V7V8V9_MMCM_SET_COMPENSATION0: Cell MMCME2_ADV of type 'MMCME2_ADV' has CLKIN1 and CLKIN2 driven from different source types. The different timing on these paths require different COMPENSATION settings which is not supported by the hardware. When using an MMCM in clock switchover mode, the two source inputs must be driven from the same type of resource. ```
linuswck added 1 commit 2023-10-11 15:25:42 +08:00 
- Fix Vivado Compilation Error [DRC REQP-119]
- MMCME2_ADV CLKIN1 and CLKIN2 are now driven from the same source type (BUFG)
sb10q merged commit 136e24f597 into master 2023-10-11 16:45:26 +08:00
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Reference: M-Labs/artiq-zynq#269
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