M-Labs
/
artiq-zynq
9
1
Fork 16
Code Issues 14 Pull Requests 1 Releases Wiki Activity

release-7: fix analyzer target for masters #234

Merged
sb10q merged 1 commits from mwojcik/artiq-zynq:fix_master_analyzer into release-7 2023-05-23 11:14:27 +08:00
Conversation 0 Commits 1 Files Changed 2
2 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/gateware/kasli_soc.py
View File

@ -311,7 +311,7 @@ class GenericMaster(SoCCore):
self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
self.csr_devices.append("routing_table")
self.submodules.rtio_analyzer = analyzer.Analyzer(self.rtio_tsc, self.rtio_core.cri,
self.submodules.rtio_analyzer = analyzer.Analyzer(self.rtio_tsc, self.cri_con.switch.slave,
self.ps7.s_axi_hp1)
self.csr_devices.append("rtio_analyzer")

2
src/gateware/zc706.py
View File

@ -320,7 +320,7 @@ class _MasterBase(SoCCore):
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj")
self.submodules.rtio_analyzer = analyzer.Analyzer(self.rtio_tsc, self.rtio_core.cri,
self.submodules.rtio_analyzer = analyzer.Analyzer(self.rtio_tsc, self.cri_con.switch.slave,
self.ps7.s_axi_hp1)
self.csr_devices.append("rtio_analyzer")