M-Labs/artiq-zynq
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Add ext0_synth0_80to125 option to the clocker config #230

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sb10q merged 1 commits from esavkin/artiq-zynq:add_80_to_125_clock_setting into master 2023-04-13 15:00:07 +08:00
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1 changed files with 19 additions and 0 deletions
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19
src/runtime/src/rtio_clocking.rs
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@ -20,6 +20,7 @@ pub enum RtioClock {
Int_150,
Ext0_Bypass,
Ext0_Synth0_10to125,
Ext0_Synth0_80to125,
Ext0_Synth0_100to125,
Ext0_Synth0_125to125,
}
@ -36,6 +37,7 @@ fn get_rtio_clock_cfg(cfg: &Config) -> RtioClock {
"ext0_bypass_125" => RtioClock::Ext0_Bypass,
"ext0_bypass_100" => RtioClock::Ext0_Bypass,
"ext0_synth0_10to125" => RtioClock::Ext0_Synth0_10to125,
"ext0_synth0_80to125" => RtioClock::Ext0_Synth0_80to125,
"ext0_synth0_100to125" => RtioClock::Ext0_Synth0_100to125,
"ext0_synth0_125to125" => RtioClock::Ext0_Synth0_125to125,
_ => {
@ -130,6 +132,23 @@ fn setup_si5324(i2c: &mut I2c, timer: &mut GlobalTimer, clk: RtioClock) {
SI5324_EXT_INPUT,
)
}
RtioClock::Ext0_Synth0_80to125 => {
// 125 MHz output from 80 MHz CLKINx reference, 611 Hz BW
info!("using 80MHz reference to make 125MHz RTIO clock with PLL");
(
si5324::FrequencySettings {
n1_hs: 4,
nc1_ls: 10,
n2_hs: 10,
n2_ls: 250,
n31: 40,
n32: 40,
bwsel: 4,
crystal_as_ckin2: false,
},
SI5324_EXT_INPUT,
)
}
RtioClock::Ext0_Synth0_100to125 => {
// 125MHz output, from 100MHz CLKINx reference, 586 Hz loop bandwidth
info!("using 100MHz reference to make 125MHz RTIO clock with PLL");