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drtio crc fix #153

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sb10q merged 1 commits from mwojcik/artiq-zynq:drtio_checksum_fix into master 2021-11-24 12:34:26 +08:00
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mwojcik commented 2021-11-24 12:33:05 +08:00
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Related to: https://github.com/m-labs/artiq/pull/1786

Recent changes also got rid of the need to swap bytes within 4-byte words. This allowed to simplify some of the code; while receiving is now identical to mainline (copy-less, straight up ready to be parsed), work buffer is still necessary for transmitting for reasons listed in the comment (unaligned writes, AXI burst not yet implemented). Still, wider (32-bit) writes are used and that also should give a slight performance boost compared to before.

Tested on ZC706 (master) and Kasli (satellite).

Related to: https://github.com/m-labs/artiq/pull/1786 Recent changes also got rid of the need to swap bytes within 4-byte words. This allowed to simplify some of the code; while receiving is now identical to mainline (copy-less, straight up ready to be parsed), work buffer is still necessary for transmitting for reasons listed in the comment (unaligned writes, AXI burst not yet implemented). Still, wider (32-bit) writes are used and that also should give a slight performance boost compared to before. Tested on ZC706 (master) and Kasli (satellite).
mwojcik added 1 commit 2021-11-24 12:33:06 +08:00
sb10q merged commit e8db2a4b49 into master 2021-11-24 12:34:26 +08:00
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Reference: M-Labs/artiq-zynq#153
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