removed simple variants from zc706 #145

Merged
sb10q merged 1 commits from mwojcik/artiq-zynq:remove_zc706_simple_variants into master 2021-10-08 20:23:56 +08:00
4 changed files with 6 additions and 44 deletions

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@ -45,7 +45,7 @@ Note: if you are using Nix channels the first time, you need to be aware of this
Pure build with Nix and execution on a remote JTAG server: Pure build with Nix and execution on a remote JTAG server:
```shell ```shell
nix-build -A zc706-simple-jtag # or zc706-nist_qc2-jtag or zc706-nist_clock-jtag nix-build -A zc706-nist_clock-jtag # or zc706-nist_qc2-jtag or zc706-nist_clock_satellite-jtag
./remote_run.sh ./remote_run.sh
``` ```

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@ -8,7 +8,7 @@ let
vivado = import <artiq-fast/vivado.nix> { inherit pkgs; }; vivado = import <artiq-fast/vivado.nix> { inherit pkgs; };
# FSBL configuration supplied by Vivado 2020.1 for these boards: # FSBL configuration supplied by Vivado 2020.1 for these boards:
fsblTargets = ["zc702" "zc706" "zed"]; fsblTargets = ["zc702" "zc706" "zed"];
sat_variants = ["satellite" "acpki_satellite" "nist_clock_satellite" "nist_qc2_satellite"]; sat_variants = ["acpki_satellite" "nist_clock_satellite" "nist_qc2_satellite"];
build = { target, variant, json ? null }: let build = { target, variant, json ? null }: let
szl = (import zynq-rs)."${target}-szl"; szl = (import zynq-rs)."${target}-szl";
fsbl = import "${zynq-rs}/nix/fsbl.nix" { fsbl = import "${zynq-rs}/nix/fsbl.nix" {
@ -133,18 +133,12 @@ let
); );
in in
( (
(build { target = "zc706"; variant = "simple"; }) //
(build { target = "zc706"; variant = "master"; }) //
(build { target = "zc706"; variant = "satellite"; }) //
(build { target = "zc706"; variant = "nist_clock"; }) // (build { target = "zc706"; variant = "nist_clock"; }) //
(build { target = "zc706"; variant = "nist_clock_master"; }) // (build { target = "zc706"; variant = "nist_clock_master"; }) //
(build { target = "zc706"; variant = "nist_clock_satellite"; }) // (build { target = "zc706"; variant = "nist_clock_satellite"; }) //
(build { target = "zc706"; variant = "nist_qc2"; }) // (build { target = "zc706"; variant = "nist_qc2"; }) //
(build { target = "zc706"; variant = "nist_qc2_master"; }) // (build { target = "zc706"; variant = "nist_qc2_master"; }) //
(build { target = "zc706"; variant = "nist_qc2_satellite"; }) // (build { target = "zc706"; variant = "nist_qc2_satellite"; }) //
(build { target = "zc706"; variant = "acpki_simple"; }) //
(build { target = "zc706"; variant = "acpki_master"; }) //
(build { target = "zc706"; variant = "acpki_satellite"; }) //
(build { target = "zc706"; variant = "acpki_nist_clock"; }) // (build { target = "zc706"; variant = "acpki_nist_clock"; }) //
(build { target = "zc706"; variant = "acpki_nist_clock_master"; }) // (build { target = "zc706"; variant = "acpki_nist_clock_master"; }) //
(build { target = "zc706"; variant = "acpki_nist_clock_satellite"; }) // (build { target = "zc706"; variant = "acpki_nist_clock_satellite"; }) //

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@ -1,5 +1,5 @@
TARGET := zc706 TARGET := zc706
GWARGS := -V simple GWARGS := -V nist_clock
all: ../build/runtime.bin all: ../build/runtime.bin

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@ -427,22 +427,6 @@ class _SatelliteBase(SoCCore):
self.csr_devices.append("routing_table") self.csr_devices.append("routing_table")
class _Simple_RTIO:
def __init__(self):
platform = self.platform
rtio_channels = []
for i in range(4):
phy = ttl_simple.Output(platform.request("user_led", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
rtio_channels.append(rtio.LogChannel())
self.add_rtio(rtio_channels)
class _NIST_CLOCK_RTIO: class _NIST_CLOCK_RTIO:
""" """
NIST clock hardware, with old backplane and 11 DDS channels NIST clock hardware, with old backplane and 11 DDS channels
@ -542,21 +526,6 @@ class _NIST_QC2_RTIO:
self.add_rtio(rtio_channels) self.add_rtio(rtio_channels)
class Simple(ZC706, _Simple_RTIO):
def __init__(self, acpki):
ZC706.__init__(self, acpki)
_Simple_RTIO.__init__(self)
class Master(_MasterBase, _Simple_RTIO):
def __init__(self, acpki):
_MasterBase.__init__(self, acpki)
_Simple_RTIO.__init__(self)
class Satellite(_SatelliteBase, _Simple_RTIO):
def __init__(self, acpki):
_SatelliteBase.__init__(self, acpki)
_Simple_RTIO.__init__(self)
class NIST_CLOCK(ZC706, _NIST_CLOCK_RTIO): class NIST_CLOCK(ZC706, _NIST_CLOCK_RTIO):
def __init__(self, acpki): def __init__(self, acpki):
ZC706.__init__(self, acpki) ZC706.__init__(self, acpki)
@ -589,8 +558,7 @@ class NIST_QC2_Satellite(_SatelliteBase, _NIST_QC2_RTIO):
_NIST_QC2_RTIO.__init__(self) _NIST_QC2_RTIO.__init__(self)
VARIANTS = {cls.__name__.lower(): cls for cls in [Simple, Master, Satellite, VARIANTS = {cls.__name__.lower(): cls for cls in [NIST_CLOCK, NIST_CLOCK_Master, NIST_CLOCK_Satellite,
NIST_CLOCK, NIST_CLOCK_Master, NIST_CLOCK_Satellite,
NIST_QC2, NIST_QC2_Master, NIST_QC2_Satellite]} NIST_QC2, NIST_QC2_Master, NIST_QC2_Satellite]}
@ -625,9 +593,9 @@ def main():
help="build Rust compiler configuration into the specified file") help="build Rust compiler configuration into the specified file")
parser.add_argument("-g", default=None, parser.add_argument("-g", default=None,
help="build gateware into the specified directory") help="build gateware into the specified directory")
parser.add_argument("-V", "--variant", default="simple", parser.add_argument("-V", "--variant", default="nist_clock",
help="variant: " help="variant: "
"[acpki_]simple/nist_clock/nist_qc2 " "[acpki_]nist_clock/nist_qc2[_master/_satellite] "
"(default: %(default)s)") "(default: %(default)s)")
args = parser.parse_args() args = parser.parse_args()