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DRTIO port - gateware #140

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sb10q merged 13 commits from mwojcik/artiq-zynq:drtio_gateware into master 2021-10-08 16:12:30 +08:00
Conversation 0 Commits 13 Files Changed 3 +3 -4
1 changed files with 3 additions and 4 deletions
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Showing only changes of commit e24ba9f886 - Show all commits

7
src/gateware/zc706.py
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@ -136,7 +136,6 @@ def prepare_zc706_platform(platform):
])
platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
return platform
class ZC706(SoCCore):
@ -145,7 +144,7 @@ class ZC706(SoCCore):
self.rustc_cfg = dict()
platform = zc706.Platform()
platform = prepare_zc706_platform(platform)
prepare_zc706_platform(platform)
ident = self.__class__.__name__
if self.acpki:
@ -199,7 +198,7 @@ class _MasterBase(SoCCore):
self.rustc_cfg = dict()
platform = zc706.Platform()
platform = prepare_zc706_platform(platform)
prepare_zc706_platform(platform)
ident = self.__class__.__name__
if self.acpki:
ident = "acpki_" + ident
@ -337,7 +336,7 @@ class _SatelliteBase(SoCCore):
self.rustc_cfg = dict()
platform = zc706.Platform()
platform = prepare_zc706_platform(platform)
prepare_zc706_platform(platform)
ident = self.__class__.__name__
if self.acpki:
ident = "acpki_" + ident