DRTIO port - gateware #140
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@ -24,7 +24,7 @@ from artiq.gateware.drtio import *
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import dma
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import analyzer
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import acpki
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import aux_controller
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import drtio_aux_controller
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class RTIOCRG(Module, AutoCSR):
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def __init__(self, platform):
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@ -24,7 +24,7 @@ from artiq.gateware.drtio import *
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import dma
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import analyzer
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import acpki
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import aux_controller
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import drtio_aux_controller
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class RTIOCRG(Module, AutoCSR):
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def __init__(self, platform, rtio_internal_clk):
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