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DRTIO port - gateware #140

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sb10q merged 13 commits from mwojcik/artiq-zynq:drtio_gateware into master 2021-10-08 16:12:30 +08:00
Conversation 0 Commits 13 Files Changed 3 +2 -2
3 changed files with 2 additions and 2 deletions
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0
src/gateware/aux_controller.py → src/gateware/drtio_aux_controller.py
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2
src/gateware/kasli_soc.py
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@ -24,7 +24,7 @@ from artiq.gateware.drtio import *
import dma import dma
import analyzer import analyzer
import acpki import acpki
import aux_controller import drtio_aux_controller
class RTIOCRG(Module, AutoCSR): class RTIOCRG(Module, AutoCSR):
def __init__(self, platform): def __init__(self, platform):

2
src/gateware/zc706.py
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@ -24,7 +24,7 @@ from artiq.gateware.drtio import *
import dma import dma
import analyzer import analyzer
import acpki import acpki
import aux_controller import drtio_aux_controller
class RTIOCRG(Module, AutoCSR): class RTIOCRG(Module, AutoCSR):
def __init__(self, platform, rtio_internal_clk): def __init__(self, platform, rtio_internal_clk):