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DRTIO port - gateware #140

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sb10q merged 13 commits from mwojcik/artiq-zynq:drtio_gateware into master 2021-10-08 16:12:30 +08:00
Conversation 0 Commits 13 Files Changed 3 +4 -4
2 changed files with 4 additions and 4 deletions
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4
src/gateware/kasli_soc.py
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@ -279,7 +279,7 @@ class GenericMaster(SoCCore):
self.drtio_cri.append(core.cri)
self.csr_devices.append(core_name)
coreaux = cdr(aux_controller.DRTIOAuxControllerBare(core.link_layer))
coreaux = cdr(drtio_aux_controller.DRTIOAuxControllerBare(core.link_layer))
setattr(self.submodules, coreaux_name, coreaux)
self.csr_devices.append(coreaux_name)
@ -412,7 +412,7 @@ class GenericSatellite(SoCCore):
self.drtio_cri.append(core.cri)
self.csr_devices.append(corerep_name)
coreaux = cdr(aux_controller.DRTIOAuxControllerBare(core.link_layer))
coreaux = cdr(drtio_aux_controller.DRTIOAuxControllerBare(core.link_layer))
setattr(self.submodules, coreaux_name, coreaux)
self.csr_devices.append(coreaux_name)

4
src/gateware/zc706.py
View File

@ -248,7 +248,7 @@ class _MasterBase(SoCCore):
self.drtio_cri.append(core.cri)
self.csr_devices.append(core_name)
coreaux = cdr(aux_controller.DRTIOAuxControllerBare(core.link_layer))
coreaux = cdr(drtio_aux_controller.DRTIOAuxControllerBare(core.link_layer))
setattr(self.submodules, coreaux_name, coreaux)
self.csr_devices.append(coreaux_name)
@ -384,7 +384,7 @@ class _SatelliteBase(SoCCore):
# Repeaters - there would be for i != 0 - however zc706 only has one SFP
# and no other means to connect to
sb10q commented 2021-10-06 13:11:31 +08:00
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There's the link on the MGT SMAs but I doubt anyone needs this. @dhslichter ?

There's the link on the MGT SMAs but I doubt anyone needs this. @dhslichter ?
coreaux = cdr(aux_controller.DRTIOAuxControllerBare(core.link_layer))
coreaux = cdr(drtio_aux_controller.DRTIOAuxControllerBare(core.link_layer))
setattr(self.submodules, coreaux_name, coreaux)
self.csr_devices.append(coreaux_name)