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DRTIO port - gateware #140

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sb10q merged 13 commits from mwojcik/artiq-zynq:drtio_gateware into master 2021-10-08 16:12:30 +08:00
Conversation 0 Commits 13 Files Changed 3 +12 -23
1 changed files with 12 additions and 23 deletions
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27
src/gateware/zc706.py
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@ -152,7 +152,7 @@ class ZC706(SoCCore):
class _MasterBase(SoCCore):
def __init__(self, acpki=False, use_si5324_33=False):
def __init__(self, acpki=False):
self.acpki = acpki
self.rustc_cfg = dict()
@ -163,10 +163,6 @@ class _MasterBase(SoCCore):
ident = "acpki_" + ident
SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident)
platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
if use_si5324_33:
platform.add_extension(si5324_fmc33)
self.sys_clk_freq = 125e6
@ -223,10 +219,7 @@ class _MasterBase(SoCCore):
self.rustc_cfg["RTIO_FREQUENCY"] = str(self.drtio_transceiver.rtio_clk_freq/1e6)
if use_si5324_33:
self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324_33").rst_n)
else:
self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n)
self.csr_devices.append("si5324_rst_n")
self.rustc_cfg["has_si5324"] = None
self.rustc_cfg["si5324_as_synthesizer"] = None
@ -290,7 +283,7 @@ class _MasterBase(SoCCore):
class _SatelliteBase(SoCCore):
def __init__(self, acpki=False, use_si5324_33=False):
def __init__(self, acpki=False):
self.acpki = acpki
self.rustc_cfg = dict()
@ -301,7 +294,6 @@ class _SatelliteBase(SoCCore):
ident = "acpki_" + ident
SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident)
if use_si5324_33:
platform.add_extension(si5324_fmc33)
self.sys_clk_freq = 125e6
@ -372,10 +364,7 @@ class _SatelliteBase(SoCCore):
platform.add_false_path_constraints(
self.ps7.cd_sys.clk, self.siphaser.mmcm_freerun_output)
self.csr_devices.append("siphaser")
if use_si5324_33:
self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324_33").rst_n)
else:
self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n)
self.csr_devices.append("si5324_rst_n")
self.rustc_cfg["has_si5324"] = None
self.rustc_cfg["has_siphaser"] = None
@ -549,12 +538,12 @@ class Simple(ZC706, _Simple_RTIO):
class Master(_MasterBase, _Simple_RTIO):
def __init__(self, acpki):
_MasterBase.__init__(self, acpki, use_si5324_33=False)
_MasterBase.__init__(self, acpki)
_Simple_RTIO.__init__(self)
class Satellite(_SatelliteBase, _Simple_RTIO):
def __init__(self, acpki):
_SatelliteBase.__init__(self, acpki, use_si5324_33=False)
_SatelliteBase.__init__(self, acpki)
_Simple_RTIO.__init__(self)
class NIST_CLOCK(ZC706, _NIST_CLOCK_RTIO):
@ -564,13 +553,13 @@ class NIST_CLOCK(ZC706, _NIST_CLOCK_RTIO):
class NIST_CLOCK_Master(_MasterBase, _NIST_CLOCK_RTIO):
def __init__(self, acpki):
_MasterBase.__init__(self, acpki, use_si5324_33=True)
_MasterBase.__init__(self, acpki)
_NIST_CLOCK_RTIO.__init__(self)
class NIST_CLOCK_Satellite(_SatelliteBase, _NIST_CLOCK_RTIO):
def __init__(self, acpki):
_SatelliteBase.__init__(self, acpki, use_si5324_33=True)
_SatelliteBase.__init__(self, acpki)
_NIST_CLOCK_RTIO.__init__(self)
class NIST_QC2(ZC706, _NIST_QC2_RTIO):
@ -580,12 +569,12 @@ class NIST_QC2(ZC706, _NIST_QC2_RTIO):
class NIST_QC2_Master(_MasterBase, _NIST_QC2_RTIO):
def __init__(self, acpki):
_MasterBase.__init__(self, acpki, use_si5324_33=True)
_MasterBase.__init__(self, acpki)
_NIST_QC2_RTIO.__init__(self)
class NIST_QC2_Satellite(_SatelliteBase, _NIST_QC2_RTIO):
def __init__(self, acpki):
_SatelliteBase.__init__(self, acpki, use_si5324_33=True)
_SatelliteBase.__init__(self, acpki)
_NIST_QC2_RTIO.__init__(self)