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Si5324 Rust driver brought on par with og artiq #132

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sb10q merged 5 commits from si5324_improvements into master 2021-08-04 09:12:38 +08:00
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src/gateware/zc706.py
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@ -82,7 +82,7 @@ class ZC706(SoCCore):
platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
self.config["HAS_SI5324"] = None
self.rustc_cfg["HAS_SI5324"] = None
self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n)
self.csr_devices.append("si5324_rst_n")