src/gateware/kasli_soc.py

@@ -108,6 +108,9 @@ class GenericStandalone(SoCCore):
         platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
         platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
 
+        self.rustc_cfg["HAS_SI5324"] = None
+        self.rustc_cfg["SI5324_SOFT_RESET"] = None
+
         self.crg = self.ps7 # HACK for eem_7series to find the clock
         self.submodules.rtio_crg = RTIOCRG(self.platform)
         self.csr_devices.append("rtio_crg")

src/gateware/zc706.py

@@ -11,6 +11,7 @@ from migen_axi.integration.soc_core import SoCCore
 from migen_axi.platforms import zc706
 from misoc.interconnect.csr import *
 from misoc.integration import cpu_interface
+from misoc.cores import gpio
 
 from artiq.gateware import rtio, nist_clock, nist_qc2
 from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, dds, spi2
@@ -81,6 +82,10 @@ class ZC706(SoCCore):
         platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
         platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
 
+        self.config["HAS_SI5324"] = None
+        self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n)
+        self.csr_devices.append("si5324_rst_n")
+
         self.submodules.rtio_crg = RTIOCRG(self.platform, self.ps7.cd_sys.clk)
         self.csr_devices.append("rtio_crg")
         self.rustc_cfg["has_rtio_crg_clock_sel"] = None

src/runtime/src/main.rs

@@ -45,7 +45,7 @@ mod mgmt;
 mod analyzer;
 mod irq;
 mod i2c;
-#[cfg(feature = "target_kasli_soc")]
+#[cfg(has_si5324)]
 mod si5324;
 
 fn init_gateware() {
@@ -162,7 +162,7 @@ async fn report_async_rtio_errors() {
     }
 }
 
-#[cfg(feature = "target_kasli_soc")]
+#[cfg(has_si5324)]
 // 125MHz output, from crystal, 7 Hz
 const SI5324_SETTINGS: si5324::FrequencySettings
     = si5324::FrequencySettings {
@@ -199,7 +199,7 @@ pub fn main_core0() {
     info!("detected gateware: {}", identifier_read(&mut [0; 64]));
 
     i2c::init();
-    #[cfg(feature = "target_kasli_soc")]
+    #[cfg(has_si5324)]
     si5324::setup(unsafe { (&mut i2c::I2C_BUS).as_mut().unwrap() },
         &SI5324_SETTINGS, si5324::Input::Ckin2, timer).expect("cannot initialize Si5324");
 

src/runtime/src/si5324.rs

@@ -2,11 +2,21 @@ use core::result;
 use log::info;
 use libboard_zynq::{i2c::I2c, timer::GlobalTimer, time::Milliseconds};
 use embedded_hal::blocking::delay::DelayUs;
+#[cfg(not(si5324_soft_reset))]
+use pl::csr;
 
 type Result<T> = result::Result<T, &'static str>;
 
 const ADDRESS: u8 = 0x68;
 
+#[cfg(not(si5324_soft_reset))]
+fn hard_reset(timer: GlobalTimer) {
+    unsafe { csr::si5324_rst_n::out_write(0); }
+    timer.delay_us(1_000);
+    unsafe { csr::si5324_rst_n::out_write(1); }
+    timer.delay_us(10_000);
+}
+
 // NOTE: the logical parameters DO NOT MAP to physical values written
 // into registers. They have to be mapped; see the datasheet.
 // DSPLLsim reports the logical parameters in the design summary, not
@@ -135,6 +145,7 @@ fn ident(i2c: &mut I2c) -> Result<u16> {
     Ok(((read(i2c, 134)? as u16) << 8) | (read(i2c, 135)? as u16))
 }
 
+#[cfg(si5324_soft_reset)]
 fn soft_reset(i2c: &mut I2c, timer: GlobalTimer) -> Result<()> {
     write_no_ack_value(i2c, 136, read(i2c, 136)? | 0x80)?;
     timer.delay_us(10_000);
@@ -170,6 +181,9 @@ fn monitor_lock(i2c: &mut I2c, timer: GlobalTimer) -> Result<()> {
 }
 
 fn init(i2c: &mut I2c, timer: GlobalTimer) -> Result<()> {
+    #[cfg(not(si5324_soft_reset))]
+    hard_reset(timer);
+
     #[cfg(feature = "target_kasli_soc")]
     {
         i2c.pca9548_select(0x70, 0)?;
@@ -180,6 +194,7 @@ fn init(i2c: &mut I2c, timer: GlobalTimer) -> Result<()> {
         return Err("Si5324 does not have expected product number");
     }
 
+    #[cfg(si5324_soft_reset)]
     soft_reset(i2c, timer)?;
     Ok(())
 }