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Regression: RTIO PLL fails to lock on with external clock on zc706 drtio master #180

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opened 2022-04-07 02:06:41 +08:00 by ljstephenson · 0 comments
ljstephenson commented 2022-04-07 02:06:41 +08:00

With a ~400mV differential clock signal at either 100MHz or 125MHz applied to the zc706 clk p/n SMAs, the standard (non-DRTIO) QC2 image (https://nixbld.m-labs.hk/build/116261) obtains a PLL lock and boots normally but the QC2 DRTIO master (https://nixbld.m-labs.hk/build/116250) does not obtain a lock, and is stuck looping.

With a ~400mV differential clock signal at either 100MHz or 125MHz applied to the zc706 clk p/n SMAs, the standard (non-DRTIO) QC2 image (https://nixbld.m-labs.hk/build/116261) obtains a PLL lock and boots normally but the QC2 DRTIO master (https://nixbld.m-labs.hk/build/116250) does not obtain a lock, and is stuck looping.
sb10q closed this issue 2022-04-13 16:42:03 +08:00
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Reference: M-Labs/artiq-zynq#180
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