zc706 master: forward sma clock to si5324 #184

Merged
sb10q merged 1 commits from mwojcik/artiq-zynq:zc706_ext_clk_fix into master 2022-04-13 16:42:03 +08:00

Fixes #180

Why some Kasli-SoC masters won't lock PLLs - still unknown. However, this PR should fix the biggest oversight with zc706.

Code shamelessly lifted from Kasli-SoC's routing.

With this change PLL locks without issue with external clock:

[     0.005266s]  INFO(runtime): detected gateware: NIST_QC2_Master
[     0.040049s]  INFO(runtime::rtio_clocking): using 125MHz reference to make 125MHz RTIO clock with PLL
[     0.389200s]  INFO(libboard_artiq::si5324): waiting for Si5324 lock...
[     3.006953s]  INFO(libboard_artiq::si5324):   ...locked
[     3.016993s]  INFO(runtime::rtio_clocking): RTIO PLL locked
Fixes #180 Why some Kasli-SoC masters won't lock PLLs - still unknown. However, this PR should fix the biggest oversight with zc706. Code shamelessly lifted from Kasli-SoC's routing. With this change PLL locks without issue with external clock: ``` [ 0.005266s] INFO(runtime): detected gateware: NIST_QC2_Master [ 0.040049s] INFO(runtime::rtio_clocking): using 125MHz reference to make 125MHz RTIO clock with PLL [ 0.389200s] INFO(libboard_artiq::si5324): waiting for Si5324 lock... [ 3.006953s] INFO(libboard_artiq::si5324): ...locked [ 3.016993s] INFO(runtime::rtio_clocking): RTIO PLL locked ```
mwojcik added 1 commit 2022-04-13 16:40:04 +08:00
sb10q merged commit 1d731a3589 into master 2022-04-13 16:42:03 +08:00
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Reference: M-Labs/artiq-zynq#184
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