move registers too

flake.lock

@@ -11,11 +11,11 @@
         "src-pythonparser": "src-pythonparser"
       },
       "locked": {
-        "lastModified": 1733894986,
-        "narHash": "sha256-zwMs87eUiVURXqavNYL42ZGi+INA7AXHUkx+go9dCLs=",
+        "lastModified": 1732066716,
+        "narHash": "sha256-krjvt9+RccnAxSEZcFhRpjA2S3CoqE4MSa1JUg421b4=",
         "ref": "refs/heads/master",
-        "rev": "3db8d2310cb45989a7fb4408508013ea1c03f7b9",
-        "revCount": 9113,
+        "rev": "270a417a28b516d36983779a1adb6d33a3c55a4a",
+        "revCount": 9102,
         "type": "git",
         "url": "https://github.com/m-labs/artiq.git"
       },
@@ -70,11 +70,11 @@
     },
     "nixpkgs": {
       "locked": {
-        "lastModified": 1733759999,
-        "narHash": "sha256-463SNPWmz46iLzJKRzO3Q2b0Aurff3U1n0nYItxq7jU=",
+        "lastModified": 1731319897,
+        "narHash": "sha256-PbABj4tnbWFMfBp6OcUK5iGy1QY+/Z96ZcLpooIbuEI=",
         "owner": "NixOS",
         "repo": "nixpkgs",
-        "rev": "a73246e2eef4c6ed172979932bc80e1404ba2d56",
+        "rev": "dc460ec76cbff0e66e269457d7b728432263166c",
         "type": "github"
       },
       "original": {
@@ -142,11 +142,11 @@
         ]
       },
       "locked": {
-        "lastModified": 1733319649,
-        "narHash": "sha256-ATJV2UV9FXEiTF6/1BvZ2HmB0goF5TZ2ytgRBwD/BGg=",
+        "lastModified": 1728371104,
+        "narHash": "sha256-PPnAyDedUQ7Og/Cby9x5OT9wMkNGTP8GS53V6N/dk4w=",
         "owner": "m-labs",
         "repo": "sipyco",
-        "rev": "27312727bdb8a182bd6e222e4cbdd3f39ae41d4e",
+        "rev": "094a6cd63ffa980ef63698920170e50dc9ba77fd",
         "type": "github"
       },
       "original": {

flake.nix

@@ -11,7 +11,6 @@
     zynqpkgs = zynq-rs.packages.x86_64-linux;
     artiqpkgs = artiq.packages.x86_64-linux;
     llvmPackages_11 = zynq-rs.llvmPackages_11;
-    zynqRev = self.sourceInfo.rev or "unknown";
 
     rust = zynq-rs.rust;
     rustPlatform = zynq-rs.rustPlatform;
@@ -138,7 +137,6 @@
           llvmPackages_11.clang-unwrapped
         ];
         buildPhase = ''
-          export ZYNQ_REV=${zynqRev}
           export XARGO_RUST_SRC="${rust}/lib/rustlib/src/rust/library"
           export CLANG_EXTRA_INCLUDE_DIR="${llvmPackages_11.clang-unwrapped.lib}/lib/clang/11.1.0/include"
           export CARGO_HOME=$(mktemp -d cargo-home.XXX)
@@ -166,7 +164,6 @@
           ];
         }
         ''
-          export ZYNQ_REV=${zynqRev}
           python ${./src/gateware}/${target}.py -g build ${if json == null then "-V ${variant}" else json}
           mkdir -p $out $out/nix-support
           cp build/top.bit $out
@@ -389,7 +386,6 @@
         binutils-arm
         pre-commit
       ];
-      ZYNQ_REV="${zynqRev}";
       XARGO_RUST_SRC = "${rust}/lib/rustlib/src/rust/library";
       CLANG_EXTRA_INCLUDE_DIR = "${llvmPackages_11.clang-unwrapped.lib}/lib/clang/11.1.0/include";
       ZYNQ_RS = "${zynq-rs}";

src/gateware/config.py

@@ -1,15 +1,5 @@
-import os
-from artiq._version import get_version
 from misoc.integration import cpu_interface
 
-
-def generate_ident(variant):
-    return "{}+{};{}".format(
-        get_version().split(".")[0],
-        os.getenv("ZYNQ_REV", default="unknown")[:8],
-        variant,
-    )
-
 def write_csr_file(soc, filename):
     with open(filename, "w") as f:
         f.write(cpu_interface.get_csr_rust(

src/gateware/ebaz4205.py

@@ -7,7 +7,7 @@ import dma
 from artiq.gateware import rtio
 from artiq.gateware.rtio.phy import spi2, ttl_simple
 from artiq.gateware.rtio.xilinx_clocking import fix_serdes_timing_path
-from config import generate_ident, write_csr_file, write_mem_file, write_rustc_cfg_file
+from config import write_csr_file, write_mem_file, write_rustc_cfg_file
 from migen import *
 from migen.build.generic_platform import IOStandard, Misc, Pins, Subsignal
 from migen.build.platforms import ebaz4205
@@ -125,7 +125,7 @@ class EBAZ4205(SoCCore):
             "set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets gmii_tx_clk_IBUF]"
         )
 
-        ident = generate_ident(self.__class__.__name__)
+        ident = self.__class__.__name__
         if self.acpki:
             ident = "acpki_" + ident
         SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident)

src/gateware/kasli_soc.py

@@ -8,7 +8,9 @@ from migen.build.generic_platform import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 from migen.genlib.cdc import MultiReg
 from migen_axi.integration.soc_core import SoCCore
+from migen_axi.interconnect import axi, axi2csr
 from migen_axi.platforms import kasli_soc
+from misoc.interconnect import csr_bus
 from misoc.interconnect.csr import *
 from misoc.cores import virtual_leds
 
@@ -24,10 +26,10 @@ from artiq.gateware.wrpll import wrpll
 
 import dma
 import analyzer
-import acpki as acpki_lib
+import acpki
 import drtio_aux_controller
 import zynq_clocking
-from config import generate_ident, write_csr_file, write_mem_file, write_rustc_cfg_file
+from config import write_csr_file, write_mem_file, write_rustc_cfg_file
 
 eem_iostandard_dict = {
      0: "LVDS_25",
@@ -115,7 +117,7 @@ class GenericStandalone(SoCCore):
         platform.toolchain.bitstream_commands.extend([
             "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
         ])
-        ident = generate_ident(description["variant"])
+        ident = description["variant"]
         if self.acpki:
             ident = "acpki_" + ident
         SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
@@ -184,10 +186,10 @@ class GenericStandalone(SoCCore):
 
         if self.acpki:
             self.config["KI_IMPL"] = "acp"
-            self.submodules.rtio = acpki_lib.KernelInitiator(self.rtio_tsc,
-                                                             bus=self.ps7.s_axi_acp,
-                                                             user=self.ps7.s_axi_acp_user,
-                                                             evento=self.ps7.event.o)
+            self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc,
+                                                         bus=self.ps7.s_axi_acp,
+                                                         user=self.ps7.s_axi_acp_user,
+                                                         evento=self.ps7.event.o)
             self.csr_devices.append("rtio")
         else:
             self.config["KI_IMPL"] = "csr"
@@ -229,7 +231,7 @@ class GenericMaster(SoCCore):
         platform.toolchain.bitstream_commands.extend([
             "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
         ])
-        ident = generate_ident(description["variant"])
+        ident = description["variant"]
         if self.acpki:
             ident = "acpki_" + ident
         SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
@@ -308,6 +310,15 @@ class GenericMaster(SoCCore):
 
         self.submodules.rtio_tsc = rtio.TSC(glbl_fine_ts_width=3)
 
+        self.submodules.drtio_axi2csr = axi2csr.AXI2CSR(
+            bus_csr=csr_bus.Interface(self.csr_data_width, self.csr_address_width),
+            bus_axi=axi.Interface.like(self.ps7.m_axi_gp0))
+
+        self.register_mem("drtio_csr", self.mem_map["axi"],
+                          4 * 2**(self.csr_address_width),
+                          self.drtio_axi2csr.bus)
+
+        self.drtio_csr_devices = []
         self.drtio_csr_group = []
         self.drtioaux_csr_group = []
         self.drtioaux_memory_group = []
@@ -325,16 +336,16 @@ class GenericMaster(SoCCore):
             core = cdr(DRTIOMaster(self.rtio_tsc, self.gt_drtio.channels[i]))
             setattr(self.submodules, core_name, core)
             self.drtio_cri.append(core.cri)
-            self.csr_devices.append(core_name)
+            self.drtio_csr_devices.append(core_name)
 
             coreaux = cdr(drtio_aux_controller.DRTIOAuxControllerBare(core.link_layer))
             setattr(self.submodules, coreaux_name, coreaux)
-            self.csr_devices.append(coreaux_name)
+            self.drtio_csr_devices.append(coreaux_name)
 
             size = coreaux.get_mem_size()
-            memory_address = self.axi2csr.register_port(coreaux.get_tx_port(), size)
-            self.axi2csr.register_port(coreaux.get_rx_port(), size)
-            self.add_memory_region(memory_name, self.mem_map["csr"] + memory_address, size * 2)
+            memory_address = self.drtio_axi2csr.register_port(coreaux.get_tx_port(), size)
+            self.drtio_axi2csr.register_port(coreaux.get_rx_port(), size)
+            self.add_memory_region(memory_name, self.mem_map["axi"] + memory_address, size * 2)
         self.config["HAS_DRTIO"] = None
         self.config["HAS_DRTIO_ROUTING"] = None
 
@@ -349,10 +360,10 @@ class GenericMaster(SoCCore):
 
         if self.acpki:
             self.config["KI_IMPL"] = "acp"
-            self.submodules.rtio = acpki_lib.KernelInitiator(self.rtio_tsc,
-                                                             bus=self.ps7.s_axi_acp,
-                                                             user=self.ps7.s_axi_acp_user,
-                                                             evento=self.ps7.event.o)
+            self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc,
+                                                         bus=self.ps7.s_axi_acp,
+                                                         user=self.ps7.s_axi_acp_user,
+                                                         evento=self.ps7.event.o)
             self.csr_devices.append("rtio")
         else:
             self.config["KI_IMPL"] = "csr"
@@ -426,6 +437,29 @@ class GenericMaster(SoCCore):
         self.add_csr_group("drtioaux", self.drtioaux_csr_group)
         self.add_memory_group("drtioaux_mem", self.drtioaux_memory_group)
 
+    def get_drtio_csr_dev_address(self, name, memory):
+        if memory is not None:
+            name = "_".join([name, memory.name_override])
+        try:
+            return self.drtio_csr_devices.index(name)
+        except ValueError:
+            return None
+
+    def do_finalize(self):
+        SoCCore.do_finalize(self)
+        self.submodules.drtio_csrbankarray = csr_bus.CSRBankArray(
+            self, self.get_drtio_csr_dev_address,
+            data_width=self.csr_data_width,
+            address_width=self.csr_address_width)
+
+        self.submodules.csrcon = csr_bus.Interconnect(
+            self.drtio_axi2csr.csr, self.drtio_csrbankarray.get_buses())
+
+        for name, csrs, mapaddr, rmap in self.drtio_csrbankarray.banks:
+            self.add_csr_region(
+                name, (self.mem_map["axi"] + 0x800 * mapaddr),
+                self.csr_data_width, csrs)
+
 
 class GenericSatellite(SoCCore):
     def __init__(self, description, acpki=False):
@@ -438,7 +472,7 @@ class GenericSatellite(SoCCore):
         platform.toolchain.bitstream_commands.extend([
             "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
         ])
-        ident = generate_ident(description["variant"])
+        ident = description["variant"]
         if self.acpki:
             ident = "acpki_" + ident
         SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
@@ -544,10 +578,10 @@ class GenericSatellite(SoCCore):
 
         if self.acpki:
             self.config["KI_IMPL"] = "acp"
-            self.submodules.rtio = acpki_lib.KernelInitiator(self.rtio_tsc,
-                                                             bus=self.ps7.s_axi_acp,
-                                                             user=self.ps7.s_axi_acp_user,
-                                                             evento=self.ps7.event.o)
+            self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc,
+                                                         bus=self.ps7.s_axi_acp,
+                                                         user=self.ps7.s_axi_acp_user,
+                                                         evento=self.ps7.event.o)
             self.csr_devices.append("rtio")
         else:
             self.config["KI_IMPL"] = "csr"

src/gateware/zc706.py

@@ -25,7 +25,7 @@ import analyzer
 import acpki
 import drtio_aux_controller
 import zynq_clocking
-from config import generate_ident, write_csr_file, write_mem_file, write_rustc_cfg_file
+from config import write_csr_file, write_mem_file, write_rustc_cfg_file
 
 class SMAClkinForward(Module):
     def __init__(self, platform):
@@ -130,7 +130,7 @@ class ZC706(SoCCore):
         platform = zc706.Platform()
         prepare_zc706_platform(platform)
 
-        ident = generate_ident(self.__class__.__name__)
+        ident = self.__class__.__name__
         if self.acpki:
             ident = "acpki_" + ident
         SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
@@ -203,7 +203,7 @@ class _MasterBase(SoCCore):
 
         platform = zc706.Platform()
         prepare_zc706_platform(platform)
-        ident = generate_ident(self.__class__.__name__)
+        ident = self.__class__.__name__
         if self.acpki:
             ident = "acpki_" + ident
         SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
@@ -344,7 +344,7 @@ class _SatelliteBase(SoCCore):
 
         platform = zc706.Platform()
         prepare_zc706_platform(platform)
-        ident = generate_ident(self.__class__.__name__)
+        ident = self.__class__.__name__
         if self.acpki:
             ident = "acpki_" + ident
         SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)

src/libboard_artiq/src/drtioaux.rs

@@ -6,7 +6,7 @@ use io::{proto::{ProtoRead, ProtoWrite},
          Cursor};
 use libboard_zynq::{time::Milliseconds, timer::GlobalTimer};
 
-pub use crate::drtioaux_proto::{Packet, MAX_PACKET};
+pub use crate::drtioaux_proto::Packet;
 use crate::{drtioaux_proto::Error as ProtocolError, mem::mem::DRTIOAUX_MEM, pl::csr::DRTIOAUX};
 
 #[derive(Debug)]
@@ -35,15 +35,6 @@ impl From<IoError> for Error {
     }
 }
 
-pub fn copy_work_buffer(src: *mut u32, dst: *mut u32, len: isize) {
-    // fix for artiq-zynq#344
-    unsafe {
-        for i in 0..(len / 4) {
-            *dst.offset(i) = *src.offset(i);
-        }
-    }
-}
-
 pub fn reset(linkno: u8) {
     let linkno = linkno as usize;
     unsafe {
@@ -124,9 +115,7 @@ where F: FnOnce(&mut [u8]) -> Result<usize, Error> {
     unsafe {
         while (DRTIOAUX[linkno].aux_tx_read)() != 0 {}
         let ptr = DRTIOAUX_MEM[linkno].base as *mut u32;
-        let mut buf: [u8; MAX_PACKET] = [0; MAX_PACKET];
-        let len = f(&mut buf)?;
-        copy_work_buffer(buf.as_mut_ptr() as *mut u32, ptr, len as isize);
+        let len = f(slice::from_raw_parts_mut(ptr as *mut u8, 0x400 as usize))?;
         (DRTIOAUX[linkno].aux_tx_length_write)(len as u16);
         (DRTIOAUX[linkno].aux_tx_write)(1);
         Ok(())

src/libboard_artiq/src/drtioaux_async.rs

@@ -9,8 +9,8 @@ use libboard_zynq::{time::Milliseconds, timer::GlobalTimer};
 use nb;
 use void::Void;
 
-pub use crate::drtioaux_proto::{Packet, MAX_PACKET};
-use crate::{drtioaux::{copy_work_buffer, has_rx_error, Error},
+pub use crate::drtioaux_proto::Packet;
+use crate::{drtioaux::{has_rx_error, Error},
             mem::mem::DRTIOAUX_MEM,
             pl::csr::DRTIOAUX};
 
@@ -102,9 +102,7 @@ where F: FnOnce(&mut [u8]) -> Result<usize, Error> {
     unsafe {
         let _ = block_async!(tx_ready(linkno)).await;
         let ptr = DRTIOAUX_MEM[linkno].base as *mut u32;
-        let mut buf: [u8; MAX_PACKET] = [0; MAX_PACKET];
-        let len = f(&mut buf)?;
-        copy_work_buffer(buf.as_mut_ptr() as *mut u32, ptr, len as isize);
+        let len = f(slice::from_raw_parts_mut(ptr as *mut u8, 0x400 as usize))?;
         (DRTIOAUX[linkno].aux_tx_length_write)(len as u16);
         (DRTIOAUX[linkno].aux_tx_write)(1);
         Ok(())

src/libboard_artiq/src/drtioaux_proto.rs

@@ -1,7 +1,7 @@
 use core_io::{Error as IoError, Read, Write};
 use io::proto::{ProtoRead, ProtoWrite};
 
-pub const MAX_PACKET: usize = 1024;
+const MAX_PACKET: usize = 1024;
 
 // maximum size of arbitrary payloads
 // used by satellite -> master analyzer, subkernel exceptions

src/runtime/src/comms.rs

@@ -10,11 +10,15 @@ use io::Cursor;
 #[cfg(has_drtio)]
 use ksupport::rpc;
 use ksupport::{kernel, resolve_channel_name};
+#[cfg(has_drtio)]
+use libasync::delay;
 use libasync::{smoltcp::{Sockets, TcpStream},
                task};
 use libboard_artiq::drtio_routing;
 #[cfg(feature = "target_kasli_soc")]
 use libboard_zynq::error_led::ErrorLED;
+#[cfg(has_drtio)]
+use libboard_zynq::time::Milliseconds;
 use libboard_zynq::{self as zynq,
                     smoltcp::{self,
                               iface::{EthernetInterfaceBuilder, NeighborCache},