move registers too

src/gateware/kasli_soc.py

@@ -8,7 +8,9 @@ from migen.build.generic_platform import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 from migen.genlib.cdc import MultiReg
 from migen_axi.integration.soc_core import SoCCore
+from migen_axi.interconnect import axi, axi2csr
 from migen_axi.platforms import kasli_soc
+from misoc.interconnect import csr_bus
 from misoc.interconnect.csr import *
 from misoc.cores import virtual_leds
 
@@ -308,6 +310,15 @@ class GenericMaster(SoCCore):
 
         self.submodules.rtio_tsc = rtio.TSC(glbl_fine_ts_width=3)
 
+        self.submodules.drtio_axi2csr = axi2csr.AXI2CSR(
+            bus_csr=csr_bus.Interface(self.csr_data_width, self.csr_address_width),
+            bus_axi=axi.Interface.like(self.ps7.m_axi_gp0))
+
+        self.register_mem("drtio_csr", self.mem_map["axi"],
+                          4 * 2**(self.csr_address_width),
+                          self.drtio_axi2csr.bus)
+
+        self.drtio_csr_devices = []
         self.drtio_csr_group = []
         self.drtioaux_csr_group = []
         self.drtioaux_memory_group = []
@@ -325,16 +336,16 @@ class GenericMaster(SoCCore):
             core = cdr(DRTIOMaster(self.rtio_tsc, self.gt_drtio.channels[i]))
             setattr(self.submodules, core_name, core)
             self.drtio_cri.append(core.cri)
-            self.csr_devices.append(core_name)
+            self.drtio_csr_devices.append(core_name)
 
             coreaux = cdr(drtio_aux_controller.DRTIOAuxControllerBare(core.link_layer))
             setattr(self.submodules, coreaux_name, coreaux)
-            self.csr_devices.append(coreaux_name)
+            self.drtio_csr_devices.append(coreaux_name)
 
             size = coreaux.get_mem_size()
-            memory_address = self.axi2csr.register_port(coreaux.get_tx_port(), size)
-            self.axi2csr.register_port(coreaux.get_rx_port(), size)
-            self.add_memory_region(memory_name, self.mem_map["csr"] + memory_address, size * 2)
+            memory_address = self.drtio_axi2csr.register_port(coreaux.get_tx_port(), size)
+            self.drtio_axi2csr.register_port(coreaux.get_rx_port(), size)
+            self.add_memory_region(memory_name, self.mem_map["axi"] + memory_address, size * 2)
         self.config["HAS_DRTIO"] = None
         self.config["HAS_DRTIO_ROUTING"] = None
 
@@ -426,6 +437,29 @@ class GenericMaster(SoCCore):
         self.add_csr_group("drtioaux", self.drtioaux_csr_group)
         self.add_memory_group("drtioaux_mem", self.drtioaux_memory_group)
 
+    def get_drtio_csr_dev_address(self, name, memory):
+        if memory is not None:
+            name = "_".join([name, memory.name_override])
+        try:
+            return self.drtio_csr_devices.index(name)
+        except ValueError:
+            return None
+
+    def do_finalize(self):
+        SoCCore.do_finalize(self)
+        self.submodules.drtio_csrbankarray = csr_bus.CSRBankArray(
+            self, self.get_drtio_csr_dev_address,
+            data_width=self.csr_data_width,
+            address_width=self.csr_address_width)
+
+        self.submodules.csrcon = csr_bus.Interconnect(
+            self.drtio_axi2csr.csr, self.drtio_csrbankarray.get_buses())
+
+        for name, csrs, mapaddr, rmap in self.drtio_csrbankarray.banks:
+            self.add_csr_region(
+                name, (self.mem_map["axi"] + 0x800 * mapaddr),
+                self.csr_data_width, csrs)
+
 
 class GenericSatellite(SoCCore):
     def __init__(self, description, acpki=False):