kasli_soc: cleanup gateware

flake.lock

@@ -2,19 +2,20 @@
   "nodes": {
     "artiq": {
       "inputs": {
+        "artiq-comtools": "artiq-comtools",
         "mozilla-overlay": "mozilla-overlay",
         "nixpkgs": "nixpkgs",
+        "sipyco": "sipyco",
         "src-migen": "src-migen",
         "src-misoc": "src-misoc",
-        "src-pythonparser": "src-pythonparser",
+        "src-pythonparser": "src-pythonparser"
-        "src-sipyco": "src-sipyco"
       },
       "locked": {
-        "lastModified": 1644375232,
+        "lastModified": 1646127620,
-        "narHash": "sha256-jd8sAlAz6xGQoxiRUV5ChtEjdjh4pdIksUPsqftcK5s=",
+        "narHash": "sha256-hiA4Qy62ZLM8aVY04RcK6eEOk2+UGR+RTPnYG3YtAg4=",
         "ref": "master",
-        "rev": "a0070d4396136b84e0a50a1c57ee72bcf4e7f6f9",
+        "rev": "17ecd355309600b997e303b41efb3d33af33c3dc",
-        "revCount": 7961,
+        "revCount": 7989,
         "type": "git",
         "url": "https://github.com/m-labs/artiq.git"
       },
@@ -23,6 +24,31 @@
         "url": "https://github.com/m-labs/artiq.git"
       }
     },
+    "artiq-comtools": {
+      "inputs": {
+        "nixpkgs": [
+          "artiq",
+          "nixpkgs"
+        ],
+        "sipyco": [
+          "artiq",
+          "sipyco"
+        ]
+      },
+      "locked": {
+        "lastModified": 1644743100,
+        "narHash": "sha256-XqxMq2l2DXSovV7r2k/FXjYRM3bvVl3Mjy+C1koVAx4=",
+        "owner": "m-labs",
+        "repo": "artiq-comtools",
+        "rev": "8a126dd7d0a3f2d50ae151ec633cd52587d98796",
+        "type": "github"
+      },
+      "original": {
+        "owner": "m-labs",
+        "repo": "artiq-comtools",
+        "type": "github"
+      }
+    },
     "mozilla-overlay": {
       "flake": false,
       "locked": {
@@ -73,11 +99,11 @@
     },
     "nixpkgs": {
       "locked": {
-        "lastModified": 1643503720,
+        "lastModified": 1644472683,
-        "narHash": "sha256-tJic20ufuRnG8V+fTCd3YU6xl1ImxNspoEkXHct0AG4=",
+        "narHash": "sha256-sP6iM4NksOYO6NFfTJ96cg+ClPnq6cdY30xKA1iYtyU=",
         "owner": "NixOS",
         "repo": "nixpkgs",
-        "rev": "0f316e4d72daed659233817ffe52bf08e081b5de",
+        "rev": "7adc9c14ec74b27358a8df9b973087e351425a79",
         "type": "github"
       },
       "original": {
@@ -94,6 +120,27 @@
         "zynq-rs": "zynq-rs"
       }
     },
+    "sipyco": {
+      "inputs": {
+        "nixpkgs": [
+          "artiq",
+          "nixpkgs"
+        ]
+      },
+      "locked": {
+        "lastModified": 1644649772,
+        "narHash": "sha256-LE9L5bDSunCPEnuf5Ed8enTAXA2vkTSmjvqPX9ILO0Y=",
+        "owner": "m-labs",
+        "repo": "sipyco",
+        "rev": "8e4382352bc64bd01c9db35d9c9b0ef42b8b9d3b",
+        "type": "github"
+      },
+      "original": {
+        "owner": "m-labs",
+        "repo": "sipyco",
+        "type": "github"
+      }
+    },
     "src-migen": {
       "flake": false,
       "locked": {
@@ -144,22 +191,6 @@
         "type": "github"
       }
     },
-    "src-sipyco": {
-      "flake": false,
-      "locked": {
-        "lastModified": 1641866796,
-        "narHash": "sha256-TSH0IgNbi9IcMcBDb2nWRphKlxstbWeATjrGbi6K2m0=",
-        "owner": "m-labs",
-        "repo": "sipyco",
-        "rev": "b04234c49379cd446d4cb3346d4741868d86841a",
-        "type": "github"
-      },
-      "original": {
-        "owner": "m-labs",
-        "repo": "sipyco",
-        "type": "github"
-      }
-    },
     "zynq-rs": {
       "inputs": {
         "mozilla-overlay": "mozilla-overlay_3",

sias3.json

@@ -0,0 +1,53 @@
+{
+    "target": "kasli_soc",
+    "min_artiq_version": "7.0",
+    "variant": "sias3",
+    "hw_rev": "v1.0",
+    "ext_ref_frequency": 125e6,
+    "base": "master",
+    "core_addr": "192.168.1.75",
+    "peripherals": [
+        {
+            "type": "grabber",
+            "ports": [1, 2]
+        },
+        {
+            "type": "dio",
+            "board": "DIO_SMA",
+            "ports": [3],
+            "bank_direction_low": "output",
+            "bank_direction_high": "output"
+        },
+        {
+            "type": "dio",
+            "board": "DIO_SMA",            
+            "ports": [4],
+            "bank_direction_low": "output",
+            "bank_direction_high": "output"
+        },
+        {
+            "type": "urukul",
+            "dds": "ad9910",
+            "ports": [5, 6],
+            "synchronization": true,
+            "clk_sel": 2
+        },
+        {
+            "type": "urukul",
+            "dds": "ad9910",
+            "ports": [7, 8],
+            "synchronization": true,
+            "clk_sel": 2
+        },
+        {
+            "type": "mirny",
+            "ports": [9],
+            "clk_sel": "mmcx",
+            "refclk": 125e6
+        },
+        {
+            "type": "sampler",
+            "ports": [10, 11]
+        }
+    ]
+}

src/gateware/kasli_soc.py

@@ -96,6 +96,19 @@ def eem_iostandard(eem):
     return IOStandard(eem_iostandard_dict[eem])
 
 
+class SMAClkinForward(Module):
+    def __init__(self, platform):
+        sma_clkin = platform.request("sma_clkin")
+        sma_clkin_se = Signal()
+        cdr_clk_se = Signal()
+        cdr_clk = platform.request("cdr_clk")
+        self.specials += [
+            Instance("IBUFDS", i_I=sma_clkin.p, i_IB=sma_clkin.n, o_O=sma_clkin_se),
+            Instance("ODDR", i_C=sma_clkin_se, i_CE=1, i_D1=1, i_D2=0, o_Q=cdr_clk_se),
+            Instance("OBUFDS", i_I=cdr_clk_se, o_O=cdr_clk.p, o_OB=cdr_clk.n)
+        ]
+
+
 class GenericStandalone(SoCCore):
     def __init__(self, description, acpki=False):
         self.acpki = acpki
@@ -113,6 +126,8 @@ class GenericStandalone(SoCCore):
         platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
         platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
 
+        self.submodules += SMAClkinForward(self.platform)
+
         self.rustc_cfg["has_si5324"] = None
         self.rustc_cfg["si5324_soft_reset"] = None
 
@@ -197,6 +212,11 @@ class GenericMaster(SoCCore):
         platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
         platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
 
+        self.submodules += SMAClkinForward(self.platform)
+
+        self.rustc_cfg["has_si5324"] = None
+        self.rustc_cfg["si5324_soft_reset"] = None
+
         data_pads = [platform.request("sfp", i) for i in range(4)]
 
         self.submodules.drtio_transceiver = gtx_7series.GTX(

src/runtime/src/rtio_clocking.rs

@@ -121,100 +121,104 @@ fn init_drtio(timer: &mut GlobalTimer)
 
 #[cfg(has_si5324)]
 fn setup_si5324(i2c: &mut I2c, timer: &mut GlobalTimer, clk: RtioClock) {
-    let si5324_settings = match clk {
+    let (si5324_settings, si5324_ref_input) = match clk {
         RtioClock::Ext0_Synth0_10to125 => { // 125 MHz output from 10 MHz CLKINx reference, 504 Hz BW
             info!("using 10MHz reference to make 125MHz RTIO clock with PLL");
-            si5324::FrequencySettings {
+            (
-                n1_hs  : 10,
+                si5324::FrequencySettings {
-                nc1_ls : 4,
+                    n1_hs  : 10,
-                n2_hs  : 10,
+                    nc1_ls : 4,
-                n2_ls  : 300,
+                    n2_hs  : 10,
-                n31    : 6,
+                    n2_ls  : 300,
-                n32    : 6,
+                    n31    : 6,
-                bwsel  : 4,
+                    n32    : 6,
-                crystal_ref: false
+                    bwsel  : 4,
-            }
+                    crystal_ref: false
+                },
+                si5324::Input::Ckin1
+            )
         },
         RtioClock::Ext0_Synth0_100to125 => { // 125MHz output, from 100MHz CLKINx reference, 586 Hz loop bandwidth
             info!("using 100MHz reference to make 125MHz RTIO clock with PLL");
-            si5324::FrequencySettings {
+            (
-                n1_hs  : 10,
+                si5324::FrequencySettings {
-                nc1_ls : 4,
+                    n1_hs  : 10,
-                n2_hs  : 10,
+                    nc1_ls : 4,
-                n2_ls  : 260,
+                    n2_hs  : 10,
-                n31    : 52,
+                    n2_ls  : 260,
-                n32    : 52,
+                    n31    : 52,
-                bwsel  : 4,
+                    n32    : 52,
-                crystal_ref: false
+                    bwsel  : 4,
-            }
+                    crystal_ref: false
+                },
+                si5324::Input::Ckin1
+            )
         },
         RtioClock::Ext0_Synth0_125to125 => { // 125MHz output, from 125MHz CLKINx reference, 606 Hz loop bandwidth
             info!("using 125MHz reference to make 125MHz RTIO clock with PLL");
-            si5324::FrequencySettings {
+            (
-                n1_hs  : 5,
+                si5324::FrequencySettings {
-                nc1_ls : 8,
+                    n1_hs  : 5,
-                n2_hs  : 7,
+                    nc1_ls : 8,
-                n2_ls  : 360,
+                    n2_hs  : 7,
-                n31    : 63,
+                    n2_ls  : 360,
-                n32    : 63,
+                    n31    : 63,
-                bwsel  : 4,
+                    n32    : 63,
-                crystal_ref: false
+                    bwsel  : 4,
-            }
+                    crystal_ref: false
+                },
+                si5324::Input::Ckin1
+            )
         },
         RtioClock::Int_150 => { // 150MHz output, from crystal
             info!("using internal 150MHz RTIO clock");
-            si5324::FrequencySettings {
+            (
-                n1_hs  : 9,
+                si5324::FrequencySettings {
-                nc1_ls : 4,
+                    n1_hs  : 9,
-                n2_hs  : 10,
+                    nc1_ls : 4,
-                n2_ls  : 33732,
+                    n2_hs  : 10,
-                n31    : 7139,
+                    n2_ls  : 33732,
-                n32    : 7139,
+                    n31    : 7139,
-                bwsel  : 3,
+                    n32    : 7139,
-                crystal_ref: true
+                    bwsel  : 3,
-            }
+                    crystal_ref: true
+                },
+                si5324::Input::Ckin2
+            )
         },
         RtioClock::Int_100 => { // 100MHz output, from crystal.
             info!("using internal 100MHz RTIO clock");
-            si5324::FrequencySettings {
+            (
-                n1_hs  : 9,
+                si5324::FrequencySettings {
-                nc1_ls : 6,
+                    n1_hs  : 9,
-                n2_hs  : 10,
+                    nc1_ls : 6,
-                n2_ls  : 33732,
+                    n2_hs  : 10,
-                n31    : 7139,
+                    n2_ls  : 33732,
-                n32    : 7139,
+                    n31    : 7139,
-                bwsel  : 3,
+                    n32    : 7139,
-                crystal_ref: true
+                    bwsel  : 3,
-            }
+                    crystal_ref: true
+                },
+                si5324::Input::Ckin2
+            )
         },
-        RtioClock::Int_125 => { // 125MHz output, from crystal, 7 Hz
+        RtioClock::Int_125 | _ => { // default: 125MHz output, from crystal, 7 Hz
             info!("using internal 125MHz RTIO clock");
-            si5324::FrequencySettings {
+            (
-                n1_hs  : 10,
+                si5324::FrequencySettings {
-                nc1_ls : 4,
+                    n1_hs  : 10,
-                n2_hs  : 10,
+                    nc1_ls : 4,
-                n2_ls  : 19972,
+                    n2_hs  : 10,
-                n31    : 4565,
+                    n2_ls  : 19972,
-                n32    : 4565,
+                    n31    : 4565,
-                bwsel  : 4,
+                    n32    : 4565,
-                crystal_ref: true
+                    bwsel  : 4,
-            }
+                    crystal_ref: true
-        }
+                },
-        _ => { // same setting  as Int_125, but fallback to default
+                si5324::Input::Ckin2
-            warn!("rtio_clock setting '{:?}' is unsupported. Falling back to default internal 125MHz RTIO clock.", clk);
+            )
-            si5324::FrequencySettings {
-                n1_hs  : 10,
-                nc1_ls : 4,
-                n2_hs  : 10,
-                n2_ls  : 19972,
-                n31    : 4565,
-                n32    : 4565,
-                bwsel  : 4,
-                crystal_ref: true
-            }
         }
     };
-    let si5324_ref_input = si5324::Input::Ckin2;
     si5324::setup(i2c, &si5324_settings, si5324_ref_input, timer).expect("cannot initialize Si5324");
 }
 
@@ -224,7 +228,7 @@ pub fn init(timer: &mut GlobalTimer, cfg: &Config) {
     #[cfg(has_si5324)]
     {
         let i2c = unsafe { (&mut i2c::I2C_BUS).as_mut().unwrap() };
-        let si5324_ext_input = si5324::Input::Ckin2;
+        let si5324_ext_input = si5324::Input::Ckin1;
         match clk {
             RtioClock::Ext0_Bypass => si5324::bypass(i2c, si5324_ext_input, timer).expect("cannot bypass Si5324"),
             _ => setup_si5324(i2c, timer, clk),